Ex Parte Zinaty et al

Board of Patent Appeals and Interferences

Jun 25, 2012

11096941 (B.P.A.I. Jun. 25, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/096,941 03/31/2005 Amir Zinaty 42P21335 3509
45209 7590 06/25/2012
MISSION/BSTZ
BLAKELY SOKOLOFF TAYLOR & ZAFMAN LLP
1279 OAKMEAD PARKWAY
SUNNYVALE, CA 94085-4040
EXAMINER
CLEARY, THOMAS J
ART UNIT PAPER NUMBER
2111
MAIL DATE DELIVERY MODE
06/25/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte AMIR ZINATY, ADIT TARMASTER, MICHAEL
DERR, and HAIM LUSTIG
____________________

Appeal 2010-002938
Application 11/096,941
Technology Center 2100
____________________

Before JOHN A. JEFFERY, THOMAS S. HAHN, and JENNIFER S. BISK,
Administrative Patent Judges.

BISK, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-002938
Application 11/096,941
2
DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1, 5-12, and 14-20. Claims 2-4 and 13 have been
canceled. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

STATEMENT OF THE CASE
The claims are directed to a mechanism for a shared serial peripheral
interface. Title. Claim 1, reproduced below with emphasis added, is
illustrative of the claimed subject matter:
1. A chipset comprising:
a memory control component; and
an input/output (I/O) control component, coupled to a
serial peripheral interface (SPI), having an arbiter to arbitrate
for control of a slave device between the I/O control component
and a master device, the SPI including a bus request signal pin
coupled between the chipset and the master device to enable the
master device to request control of the SPI from the arbiter.

THE REJECTIONS
1. Claims 1 and 7-12 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Rothman (US 2006/0184717 A1; Aug. 17, 2006 (filed
Feb. 15, 2005)) and Elms (US 5,270,898; Dec. 14, 1993). Ans. 3-7.
2. Claims 17-20 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Elms. Ans. 7-8.
3. Claims 1, 5-12, and 14-16 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over England (US 6,938,164 B1; Aug. 30, 2005 (filed
Nov. 22, 2000)) and Elms. Ans. 8-13.
Appeal 2010-002938
Application 11/096,941
3

THE ANTICIPATION REJECTION

The Examiner finds that Rothman discloses every element of
representative claim 1. Ans. 4. The Examiner relies on Elms to provide
evidence that Rothman inherently discloses the features of a serial peripheral
interface (SPI) not explicitly disclosed by Rothman. Ans. 4.
Appellants argue that the chipset described in Rothman does not
disclose having a memory control component. Br. 8. Appellants also argue
that Rothman does not disclose the SPI including a “bus request signal pin
coupled between the chipset and the master device to enable the master
device to request control of the SPI from the arbiter.” Br. 9.

ISSUE
Under § 102, has the Examiner erred in rejecting claims 1 and 7-12 by
finding that Rothman discloses, either explicitly or inherently, (1) a chipset
with a memory control component, and (2) a “bus request signal pin coupled
between the chipset and the master device to enable the master device to
request control of the SPI from the arbiter”?

ANALYSIS
Based on the record before us, we find no error in the Examiner’s
anticipation rejection of claims 1 and 7-12. Appellants argue that the
Examiner erred in mapping Rothman Figure 1, Number 106 (see figure
reproduced below) to the claimed “memory control component” because it is
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Appeal 2010-002938
Application 11/096,941
5
The Examiner finds that Rothman’s flash memory 106 meets the
claimed limitation of “a memory control component” because “it is well
known in the memory arts that flash memories . . . must have internal control
components to translate and interpret signals received from a bus (such as
the SPI bus 126 of Rothman) into signals for reading to or writing from
specific memory locations.” Ans. 14. Further, the Examiner finds that the
broadest reasonable interpretation of “chipset” is “a collection of integrated
circuits that are designed to be used together for some specific purpose.”
Ans. 15. We agree with this interpretation.2 Based on this interpretation, the
Examiner equates Number 132 of Figure 1 to the claimed “chipset.” Id.
Finally, the Examiner reasonably concludes that since the flash memory
includes a memory controller and is also part of the chipset in Figure 1,
Rothman discloses a chipset having a memory control component. Id.
The Examiner has therefore presented a prima facie case of
unpatentability. See In re Jung, 637 F.3d 1356, 1362 (Fed. Cir. 2011)
(holding that the PTO satisfies the initial burden of showing a prima facie
case of anticipation unless the rejection “is so uninformative that it prevents
the applicant from recognizing and seeking to counter the grounds for
rejection.”). Therefore the burden shifts to the Appellants to rebut the
Examiner’s case. In re King, 801 F.2d 1324, 1327 (Fed. Cir. 1986).
Appellants have not satisfied this burden. In fact, Appellants do not
specifically address the above mentioned findings. See Br. 7-8.
We also are not persuaded by Appellants’ argument that Rothman
does not inherently disclose the required bus request signal pin because the

2 Chipset: “A set of integrated circuits intended to be used together.”
BARRON’S DICTIONARY OF COMPUTER AND INTERNET TERMS 81 (6th ed.
1998).
Appeal 2010-002938
Application 11/096,941
6
element is not disclosed by either the SPI bus standard or Elms. Br. 9.
Specifically, Appellants argue that “[t]here is no disclosure, or reasonable
suggestion, of the SSN pin [in Elms] being used for arbitration between two
master devices for control of an SPI.” Br. 10. However, we find reasonable
the Examiner’s finding that “Rothman is a multi-master (Elements 110 and
114) SPI system, and thus must necessarily use the features of multi-master
SPI, which are disclosed by Elms.” Ans. 15. The Examiner also points to a
portion of Elms, which “refers to the use of the SSN pin to request
mastership (control) of the bus,” and reasonably concludes that the SSN pin
is used for arbitration of control of a multiple master system. Ans. 15-16
(citing Elms col. 34, ll. 29-39). Again, the Examiner has presented a prima
facie case of unpatentability, which Appellants do not persuasively address.
See Br. 9-10.
For these reasons, we sustain the Examiner’s anticipation rejection of
representative claim 1 and claims 7-12, which were not argued separately.
Br. 10.
Appellants rely on the arguments made with respect to claim 1 to
assert that Elms does anticipate claims 17-20 because it does not disclose the
recited “bus request signal component coupled between two master
devices.” Br. 11. For the reasons discussed above, we are not persuaded by
this argument and we sustain the rejection of claims 17-20.

THE OBVIOUSNESS REJECTION3
The Examiner finds that England discloses every element of claims 1,
5-12, and 14-16 except the type of peripheral device, “an arbiter to arbitrate

3 Appellants include claim 4 in their discussion of the obviousness rejection
(Br. 12-13), however claim 4 has been canceled. Ans. 18.
Appeal 2010-002938
Application 11/096,941
7
for control of a slave device between the I/O component and a master
device,” and “a bus request signal pin coupled between the chipset and the
master device to enable the master device to request control of the peripheral
interface from the arbiter.” Ans. 8. The Examiner cites Elms as teaching
these limitations. Ans. 8-9.
Appellants argue that the combination of England and Elms does not
disclose a “bus request signal pin coupled between two masters to enable a
first master to request control of the SPI from the second master.” Br. 12-13.

ISSUE
Under § 103, has the Examiner erred in rejecting claims 1, 5-12, and
14-16 by finding that the combination of England and Elms discloses or
suggests a bus request signal pin coupled between two masters to enable the
first master to request control of the SPI from the second master?

ANALYSIS
Based on the record before us, we find no error in the Examiner’s
obviousness rejection. Appellants argue that neither Elms nor England
teaches the limitation at issue. Br. 12-13. Appellants rely on the same
arguments regarding Elms presented with respect to the anticipation
rejection. Br. 12. For the reasons discussed above, we are not persuaded by
these arguments. Appellants add that England does not disclose or suggest
this limitation. Br. 13. However, this argument is irrelevant since the
Examiner cited Elms as teaching this limitation. Ans. 8-9.
Thus, we sustain the Examiner’s obviousness rejection of
representative claim 1 and claims 5-12 and 14-16, which are not argued
separately. Br. 13.
Appeal 2010-002938
Application 11/096,941
8
DECISION
The Examiner’s decision to reject claims 1, 5-12, and 14-20 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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