Ex Parte Zhou et al

Board of Patent Appeals and Interferences

Mar 18, 2010

11230786 (B.P.A.I. Mar. 18, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte DACHENG ZHOU, JEFFRY YETTER,
and DANIEL A. BERKRAM

_____________

Appeal 2009-001778
Application 11/230,786
Technology Center 2800
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Decided: March 18, 2010
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Before JOHN C. MARTIN, ELENI MANTIS MERCADER,
and BRADLEY W. BAUMEISTER, Administrative Patent Judges.

MANTIS MERCADER, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2009-001778
Application 11/230,786

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STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Final Rejection
of claims 1, 2, 4-6, 8-16, 18-24, and 26-30. We have jurisdiction under 35
U.S.C. § 6(b).
We reverse.
INVENTION
Appellants’ claimed invention is directed to a bias voltage generation
circuit having a voltage-to-current translation circuit embodied as an n-
channel MOSFET Q1 which converts voltage 36 to a first current I1 ([0040],
Fig. 9), a current mirror circuit which includes the first and second p-channel
MOSFETs Q2 and Q3 producing a second current I2 ([0042], Fig. 9), and a
current-to-voltage translation circuit embodied as an n-channel MOSFET Q4
([0044], Fig. 9). Figure 9 is reproduced below.

Figure 9 depicts the bias voltage generation circuit.
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Application 11/230,786

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As shown in Figure 9, the drains of Q2 and Q3 are coupled together to
generate a positive interpolator bias signal 102 which is then provided to the
interpolator 200 to control a resistive load circuit as shown in Figure 10
([0043], [0045], [0046]). Furthermore, as a result of the second current I2,
the drain and gate of Q4 produce a second bias voltage, such as a negative
interpolator bias signal 104 ([0044]). The negative interpolator bias signal
104 is provided to the phase interpolator 200 coupled with the source of each
of a set of n-channel MOSFETs QS0-QS31 employed in a current weighting
circuit as shown in Figure 10 ([0044], [0045]). Figure 10 is reproduced
below.

Figure 10 depicts the positive interpolator bias signal 102 and the
negative interpolator bias signal 104 provided to the phase
interpolator 200.

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Application 11/230,786

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Claim 1, reproduced below, is representative of the subject matter on appeal:
1. A bias voltage generation circuit for a phase interpolator, the bias
voltage generation circuit comprising:
a voltage-to-current translation circuit configured to generate a first
current that is positively related to a first voltage;
a current mirror circuit configured to generate a first bias voltage that
is negatively related to the first current, and configured to generate a second
current that is positively related to the first current;
a current-to-voltage translation circuit configured to generate a second
bias voltage that is positively related to the second current; and
a resistive load circuit configured to provide a resistance coupled with
an output clock signal of the phase interpolator;
wherein the first bias voltage controls the resistive load circuit; and
wherein the second bias voltage controls a current weighting circuit of
the phase interpolator.

THE REJECTION
The Examiner relies upon the following as evidence of unpatentability:
Morishita US 2004/0027194 A1 Feb. 12, 2004
(filed Jan. 6, 2003)

The following rejection is before us for review:
The Examiner rejected claims 1, 2, 4-6, 8-16, 18-24, and 26-30 under
35 U.S.C. § 102(b) as being anticipated by Morishita.

ISSUE
The pivotal issue is whether Morishita teaches a first bias voltage
which controls a resistive load circuit.

Appeal 2009-001778
Application 11/230,786

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FINDINGS OF FACT (FF)
The following findings of fact are supported by a preponderance of the
evidence:
Morishita’s Figure 16 is reproduced below:

Figure 16 depicts a voltage adjusting circuit 300 employed in the ring
oscillator circuit.

1. Morishita teaches an Na node (Fig. 16) which is in the same circuit
location as Appellants’ node that generates first bias voltage 102 (Fig.
9).
2. Morishita also teaches a bias voltage at the Nb node (Fig. 16), which is
in the same circuit location as Appellants’ node that generates second
bias voltage 104 (Fig. 9).
3. Morishita’s bias voltage at Nb (i.e., Vout) (Fig. 16) controls a ring
oscillator circuit of Figure 15.

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Application 11/230,786

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PRINCIPLES OF LAW
“A claim is anticipated only if each and every element as set forth in
the claim is found, either expressly or inherently described, in a single prior
art reference.” Verdegaal Bros., Inc. v. Union Oil Co. of Cal., 814 F.2d 628,
631 (Fed. Cir. 1987).

ANALYSIS
Appellants argue, inter alia, that claim 1 distinguishes the first and
second bias voltages based upon which part of the bias voltage generation
circuit (i.e., the current mirror circuit or the current-to-voltage translation
circuit) generates the bias voltages (App. Br. 9). Appellants further argue
that claim 1 specifically provides for the first bias voltage to control the
resistive load circuit (App. Br. 9). Appellants also argue that the voltage at
node Na of the voltage adjusting circuit 300 of Morishita is not employed as
a bias voltage for any circuit (App. Br. 9). Accordingly, based on
Appellants’ contentions, Appellants essentially argue that Morishita does not
teach a first bias voltage which controls a resistive load circuit as claimed.
We are persuaded by Appellants’ arguments. Morishita teaches a
node Na which is in the same circuit location as Appellants’ node that
generates first bias voltage 102 (FF 1). Morishita also teaches a second bias
voltage at the Nb node, which is in the same circuit location as Appellants’
second bias voltage 104 (FF 2). However, Morishita does not teach that
node Na generates a first bias voltage which controls a resistive load circuit.
We could not find a resistive load circuit in Morishita’s Figures 15 or 16.
Nor did the Examiner provide any evidence of a first bias voltage controlling
a resistive load circuit. Figure 15 is reproduced below.
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Figure 15 depicts a ring oscillator circuit (i.e., current weighting
circuit) for generating refresh clock signals having a voltage input Vout
generated by the voltage adjusting circuit 300.

We agree with the Examiner that Morishita’s bias voltage at Nb (i.e.,
Vout) (Fig. 16) controls a ring oscillator circuit (i.e., current weighting
circuit) of Figure 15 (FF 3). However, even if we agreed with the
Examiner’s reasoning that the voltage at Morishita’s node Na controls the
current weighting circuit by controlling the voltage at Nb (Ans. 10, Fig. 16
and Fig. 15), the Examiner has provided no evidence, nor can we find such
evidence on the record before us, that the voltage at Morishita’s node Na is
also employed to control a resistive load circuit, as required by claim 1.
For the foregoing reasons, we will reverse the Examiner’s rejection of
claim 1 and for similar reasons the rejection of claims 2, 4-6, 8-16, 18-24,
and 26-30.
Appeal 2009-001778
Application 11/230,786

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CONCLUSION
Morishita does not teach a first bias voltage which controls a resistive
load circuit.

ORDER
The decision of the Examiner to reject claims 1, 2, 4-6, 8-16, 18-24,
and 26-30 is reversed.

REVERSED

ELD

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