13668077 (P.T.A.B. Nov. 15, 2016)

Ex Parte Zhang et al

Patent Trial and Appeal BoardNov 15, 2016

13668077 (P.T.A.B. Nov. 15, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 13/668,077 11102/2012 102324 7590 11/17/2016 Artegis Law Group, LLP/NVIDIA 7710 Cherry Park Drive Suite T #104 Houston, TX 77095 FIRST NAMED INVENTOR Leilei Zhang UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. NVDA/SC-12-0130-US 7015 EXAMINER NGUYEN, DILINH P ART UNIT PAPER NUMBER 2893 NOTIFICATION DATE DELIVERY MODE 11/17/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): kcruz@artegislaw.com ALGdocketing@artegislaw.com mmccauley@artegislaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte NVIDIA CORPORATION1 Appellant Appeal2015-005752 Application 13/668,077 Technology Center 2800 Before JAMES C. HOUSEL, CHRISTOPHER L. OGDEN, and JEFFREY R. SNAY, Administrative Patent Judges. OGDEN, Administrative Patent Judge. DECISION ON APPEAL Appellant appeals under 35 U.S.C. Â§ 134(a) from the Examiner's decision2 rejecting claims 1-20 in the above-identified application. We have jurisdiction pursuant to 35 U.S.C. Â§ 6(b ). We REVERSE. 1 NVIDIA Corporation is the applicant under 37 C.F.R. i-f 1.46 (2012), and is identified as the real party in interest. Appeal Br. 3, Oct. 14, 2014. 2 Office Action, Feb. 10, 2014 [hereinafter Final Action]. Appeal2015-005752 Application 13/668,077 BACKGROlH~D Appellant's invention is directed to improving the planarity of an integrated circuit package. See Specification i-f 1, Nov. 2, 2012 [hereinafter Spec.]. The Specification discusses the use of stiffening microstructures used in the prior art, see id. i-f 4, an example of which is shown in Figure 1, reproduced below: 1tJO~ .. Â·~ 180 \ i~1 It ' \ 151 .~ ~ """ â€¢""" """ ..... ., ...... ....... ...... . ...... j...... -Â·- --Â· ---., ,f ~ ~ / /::::~ __ :::::: ... =---=--=-- - - - ! - .,.... ""\ \ \ , I : \ , Â·. 1 ... i \ \ 150 102. i i : \ \ ./ ms ~. 1' l ..... ! i110\ . ,.,.-- . _ .. / FIG. 1 PRIOR ART Figure 1 is a schematic cross-sectional view depicting a prior art packaged semiconductor device, which includes a stiffening microstructure 150. See id. i-fi-1 5--6. According to the Specification, "The stiffening microstructure 150 provides tensional rigidity to the packaging substrate 100 to promote 2 Appeal2015-005752 Application 13/668,077 planarity," and "is fastened to a chip mounting surface 110 of the substrate structure 125." Id. i-f 7. Figure 3, representing an embodiment of Appellant's invention, see id. i-f 18, is reproduced below: 3:20 l / FIG. 3 Figure 3 depicts a stiffening microstructure 351, which "may be fabricated from a rigid material, such as stainless steel, aluminum, among others." 3 Appeal2015-005752 Application 13/668,077 Amended Specification i129, Oct. 17, 2013 [hereinafter Am. Spec.]. The stiffening microstructure 351 includes a base 302 that at least partially fits inside an opening 250 of the substrate structure 200. See id. According to the Specification, this configuration is more warp resistant compared to conventional packaging sub- strates. Greater control of warping is gained through a larger stiffening microstructure and an increase contact area between the stiffening microstructure and the packaging substrate without increasing the overall height of the packaged chip. With the bot- tom of the stiffening microstructure extending below the chip mounting surface of the packaging substrate, the sectional profile of the stiffening microstructure can be selected to enhance tor- sional rigidity of the stiffening microstructure and thus provide greater warpage control for the packaging substrate. Id. if 22. Independent claim 1 is representative of the claims on appeal: 1. A packaging substrate comprising: a packaging structure having a chip mounting surface and a bottom surface, the packaging structure having at a plurality of conductive paths formed between the chip mounting surface and the bottom surface, the conductive paths providing electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface, the packaging structure having an opening formed in the chip mounting surface proximate a perimeter of the packaging structure; and a stiffening microstructure disposed in the opening and coupled to the packaging structure. Appeal Br. 13 (emphasis added). Independent claim 14 similarly includes a "stiffening microstructure disposed in the opening and coupled to the packaging structure," id. at 15. 4 Appeal2015-005752 Application 13/668,077 The Examiner maintains the following grounds of rejection: 1. Claims 1-3, 7-9, and 11 are rejected under 35 U.S.C. Â§ 102(b) as being anticipated by U.S. Patent Application Pub. No. US 2010/0308451 Al (published Dec. 9, 2010) [hereinafter Kodani]. See Final Action 3--4. 2. Claims 4--6, 10, and 14--20 are rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Kodani, and further in view of the admitted prior art in Appellant's Figure 1. See Final Action 5-8. 3. Claims 12 and 13 are rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Kodani in view of U.S. Patent No. US 6,297,550 Bl (issued Oct. 2, 2001 ). See Final Action 8-9. DISCUSSION The Examiner finds that Kodani discloses a stiffening microstructure disposed in the opening and coupled to the packaging structure, as required by claims 1 and 14. Final Action 4, 6 (citing Kodani Fig. 11 ). Figure 11 of Kodani is reproduced below: FIG. 11 20.A " \ ' ~ 2 ,., .j JOA 5 Appeal2015-005752 Application 13/668,077 Figure 11 depicts a semiconductor package in which the electrode pad 6 or 6a is exposed from the surface of an insulating interlayer 14 of packaging structure 20A. See Kodani i-f 107. The Examiner finds that electrode pads 6 of Kodani [Fig. 11] are disposed in the openings of the packaging structure 20A and located at the peripheral re- gions of the chip mounting surface. Therefore, the electrode pads 6 of Kodani, similar to the claimed structure of the present in- vention, are capable of providing stiffness to the package of Ko- dani. Answer 2. The Examiner also finds that "[ s ]ince the materials employed in making electrode pads 6 of Kodani are rigid materials such as Au, Ni, Cu and Pd (paragraph 0077), it is reasonable to assume that the electrode pads 6 of Kodani can be interpreted as stiffening micro structures, which is consistent with the Appellants' disclosure." Id. at 3. Thus, the Examiner finds that the "stiffening" limitation of claims 1 and 14 is inherently present in Kodani. See Answer 2-3. We interpret claims 1 and 14 according to the broadest reasonable construction in light of the Specification. See In re Man Machine Interface Techs. LLC, 822 F.3d 1282, 1287 (Fed. Cir. 2016). In addition, our interpretation "must be consistent with the one that those skilled in the art would reach." In re Cortright, 165 F.3d 1353, 1358 (Fed. Cir. 1999). According to the Specification, the invention reflects an improvement over surface-mounted stiffening microstructures, such as the structure 150 depicted in Figure 1, by incorporating the microstructure into an opening in the chip mounting surface. See Spec. i-fi-1 4--12, 22. The term stiffening, as used in the Specification, is a relative term. For example, any solid material could be considered "stiffening" in comparison to air or a vacuum. However, it is not reasonable, in view of the Specification, to interpret the 6 Appeal2015-005752 Application 13/668,077 term stiffening microstructure to simply mean any microstructure. The Specification indicates that the purpose of the stiffening micro structure is to "provide[] tensional rigidity to the packaging structure." See id. i-f 7. This added stiffness is in comparison to the packaging structure material excavated to make room for the stiffening microstructure. See, e.g., Spec. i-fi-13--4, 7, 22. Thus, the broadest reasonable interpretation of the term stiffening microstructure is a microstructure that adds stiffness to the package in comparison to the material excavated by the opening. In light of this interpretation, we are not persuaded that Kodani inherently discloses a stiffening microstructure. In order for a claim to be rejected on the basis of an inherent disclosure in the prior art, the required limitation must be necessarily present in the prior art. See In re Robertson, 169 F.3d 743, 745 (Fed. Cir. 1999). However, Kodani discloses that as a result of the structure and dimensions of the electrode pads and the packaging substrate, "stress or strain imposed on the electrode pads 4a and 6a, the external connection terminals 22, and the connection portion 23b can be prevented, and the reliability of the semiconductor package 30A can be improved." Appeal Br. 10 (citing Kodani i-f 109). In light of this disclosure, we are not persuaded that the electrode pads 6a in Kodani necessarily add appreciable stiffness to the package in comparison to the material of the insulating interlayer 14 in which the electrode pads are formed. Therefore, by a preponderance of the evidence on this appeal record, we are persuaded that the Examiner reversibly erred in rejecting claims 1 and 14. The rejections of claims 2-13 and 15-20 do not remedy this error. Thus, we reverse the Examiner's decision to reject claims 1-20. 7 Appeal2015-005752 Application 13/668,077 DECISION The Examiner's decision is reversed. REVERSED 8