Ex Parte Zhang et alDownload PDFPatent Trial and Appeal BoardMay 3, 201613438902 (P.T.A.B. May. 3, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 13/438,902 04/04/2012 27820 7590 05/05/2016 WITHROW & TERRANOVA, PLLC 106 Pinedale Springs Way Cary, NC 27511 FIRST NAMED INVENTOR Qingchun Zhang UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 1194-112 2831 EXAMINER AHMED, SHARED ART UNIT PAPER NUMBER 2823 NOTIFICATION DATE DELIVERY MODE 05/05/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): patents@wt-ip.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte QINGCHUN ZHANG, ANANT K. AGARWAL, and LIN CHENG Appeal2015-000039 Application 13/438,902 Technology Center 2800 Before JESSICA C. KAISER, KARA L. SZPONDOWSKI, and SHARON PENICK, Administrative Patent Judges. KAISER, Administrative Patent Judge. DECISION ON APPEAL Appellants 1 appeal under 35 U.S.C. § 134(a) from the Examiner's final rejection of claims 1-11 and 13-19.2 We have jurisdiction under 35 U.S.C. § 6(b). We affirm-in-part. 1 According to Appellants, the real party in interest is Cree, Inc. (App. Br. 1.) 2 The Examiner finds claims 20-34 are allowable and claim 12 would be allowable if rewritten in independent form. (Final Act. 1, 4, 8-9.) Appeal2015-000039 Application 13/438,902 EXEMPLARY CLAIM Claim 1 is exemplary and is reproduced below: 1. A bipolar junction transistor comprising: a collector layer; a recess region embedded in the collector layer, such that the recess region is a first type of semiconductor material and is below a base-collector plane; a base layer on the collector layer, such that the base layer is the first type of semiconductor material and the base-collector plane is between the base layer and the collector layer; and a first emitter layer on the base layer. REJECTION The Examiner has rejected claims 1-11 and 13-19 under 35 U.S.C. § 102(b) as anticipated by Veliadis (US 8,105,911 B2; issued Jan. 31, 2012). (Final Act. 5-8.) ISSUES The issues raised by Appellants' arguments are: Did the Examiner err in finding Veliadis discloses "a recess region embedded in the collector layer, such that the recess region is a first type of semiconductor material and is below a base-collector plane," as recited in claim 1? Did the Examiner err in finding Veliadis discloses "a second emitter layer on the first emitter layer," as recited in dependent claim 16? 2 Appeal2015-000039 Application 13/438,902 ANALYSIS Claims 1-11, 13-15, and 17-19 We have reviewed the Examiner's rejections in light of Appellants' arguments that the Examiner has erred. We disagree with Appellants' conclusions regarding the Examiner's rejection of claim 1. In so far as they relate to issues raised in this appeal regarding claim 1, we adopt as our own the findings and reasons set forth by the Examiner in the Final Action from which the appeal is taken and the reasons set forth in the Examiner's Answer in response to Appellants' Appeal Brief (see Ans. 2-5). We highlight and address specific findings and arguments for emphasis as follows. Appellants argue the Examiner errs in finding V eliadis discloses "a bipolar junction transistor having a recess region that is a first type of semiconductor material embedded in a collector layer of the transistor below a base-collector plane," as recited in claim 1. (App. Br. 3---6.) Specifically, Appellants argue V eliadis' trenches and guard ring edge termination structures do not disclose the recited "recess region" because the trenches are electrically isolated from the device. (See id. at 4.) In contrast, Appellants argue the recited "recess region" "electrically connects to the emitter for avalanche improvement." (Id. at 4--5.) We are unpersuaded of Examiner error. Figure 7 of Veliadis as annotated by the Examiner (Ans. 4) is reproduced below. 3 Appeal2015-000039 Application 13/438,902 1.20 -........-~·-·_,.. r~~;:~~ss r~;9H:~n \~·~hth F~ type ~rnbc.~~:ideci ·if'$ Figure 7 of Veliadis depicts an embodiment of a bipolar junction transistor 700. As shown in annotated Figure 7, the Examiner finds, and we agree, recess region 710 discloses the recited "recess region." (Ans. 2--4.) In particular, we agree with the Examiner (id.) that region 710 is "embedded in the collector layer," is "below a base-collector plane" (i.e., the plane "between the base layer and the collector layer"), and is a first type of semiconductor material (i.e., P-type ). 3 3 The Examiner finds Veliadis discloses the base layer is also a first type of semiconductor material (i.e., P-type). (Final Act. 5 (citing Veliadis 4:64-- 65).) 4 Appeal2015-000039 Application 13/438,902 We observe that Appellants' arguments (App. Br. 3---6) are not commensurate with the scope of claim 1, which is silent regarding avalanche improvement or an electrical connection between the recess region and the emitter. In addition, we find Appellants' argument that "the disclosure of Veliadis is not capable of operating as a point of avalanche" (App. Br. 5) unpersuasive because it relies only on attorney argument, which is not evidence. See In re Pearson, 494 F.2d 1399, 1405 (CCPA 1974) ("Attorney's argument in a brief cannot take the place of evidence."). Appellants argue the trench in V eliadis is "not a first type of semiconductor material, where a base layer is also of the first type of semiconductor material ... [because] the trench is filled with isolation dielectrics, which are clearly different from a material used to form the base that is disclosed in Figure 7." (App. Br. 6; see also Reply Br. 5.) We agree with the Examiner that claim 1 does not preclude isolation dielectric regions 720 in annotated Figure 7 above. (Ans. 3.) In addition, Appellants' argument is not responsive to the Examiner's findings. In particular, the Examiner finds the recessed region 710 which is a P-type semiconductor material, not the portion of the trench filled with isolation dielectrics, discloses the recited "recessed region." (Final Act 5; Ans. 2-3.) For the reasons discussed above, we sustain the Examiner's§ 102 rejection ofclaim 1 and claims 2-11, 13-15, and 17-19, not argued separately (App. Br. 6). Claim 16 Claim 16 depends from claim 1 and recites "[ t ]he bipolar junction transistor of claim 1 further comprising a second emitter layer on the first 5 Appeal2015-000039 Application 13/438,902 emitter layer." Appellants argue the Examiner errs in finding Veliadis discloses this limitation of claim 16. (App. Br. 7; Reply Br. 5---6.) We agree with Appellants' argument. The Examiner finds that in Veliadis' Figure 7, the metal layer on emitter layer 730 (as shown in the annotated Figure 7 above) discloses the recited "second emitter layer." (Ans. 4, 6.) The Examiner also finds that Veliadis discloses that "additional layers may be included to achieve an optimal BJT [(bipolar junction transistor)] design." (Id. at 6 (quoting Veliadis 5: 1-3 ). ) We determine these findings are insufficient to support an anticipation rejection of claim 16. Specifically, the Examiner does not sufficiently show that Veliadis discloses the metal layer is an emitter layer. Additionally, while column 5 of Veliadis might suggest that a second emitter layer could be used, such a suggestion is insufficient to support an anticipation rejection. See, e.g., In re Robertson, 169 F.3d 743, 745 (Fed. Cir. 1999) ("Inherency, however, may not be established by probabilities or possibilities. The mere fact that a certain thing may result from a given set of circumstances is not sufficient.") (citations omitted). For the reasons discussed above, we are constrained by the record to reverse the Examiner's decision to reject dependent claim 16. DECISION We affirm the Examiner's decision to reject claims 1-11, 13-15, and 17-19 under 35 U.S.C. § 102(b). We reverse the Examiner's decision to reject claim 16 under 3 5 U.S.C. § 102(b). 6 Appeal2015-000039 Application 13/438,902 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv). AFFIRMED-IN-PART 7 Copy with citationCopy as parenthetical citation