Ex Parte Zhang et al

Patent Trial and Appeal Board

Jun 1, 2016

13483100 (P.T.A.B. Jun. 1, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/483, 100 05/30/2012
57299 7590 06/03/2016
Kathy Manke
A vago Technologies Limited
4380 Ziegler Road
Fort Collins, CO 80525
FIRST NAMED INVENTOR
Fan Zhang
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
AGERE-034000(Ll 1-2394) 6899
EXAMINER
KOETH, MICHELLE M
ART UNIT PAPER NUMBER
2632
NOTIFICATION DATE DELIVERY MODE
06/03/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
kathy.manke@broadcom.com
patent.info@broadcom.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte FAN ZHANG, CHUNG-LI WANG, SHAO HUA YANG,
YANG HAN, XUEBIN WU, HAIT AO XIA, MING JIN
Appeal2014-007345
Application 13/483, 100
Technology Center 2600
Before CARL W. WHITEHEAD JR., JOHN F. HORVATH and
ADAM J. PYONIN, Administrative Patent Judges.
WHITEHEAD JR., Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants are appealing the final rejection of claims 1-20 under 35
U.S.C. § 134(a). Appeal Brief 4. We have jurisdiction under 35 U.S.C.
§ 6(b) (2012).
We affirm.
Introduction
"The present invention is related to systems and methods for data
processing system characterization." Abstract.
Appeal2014-007345
Application 13/483,100
Representative Claim (disputed limitations emphasized)
1. A data processing system, the data processing system comprising:
a data processing circuit, wherein the data processing circuit includes:
a data detector circuit operable to apply a data detection
algorithm to a sample data set to yield a detected output;
a detected output error count circuit operable to generate an
output side error count corresponding to a number of errors
remaining in the detected output, wherein the detected output error
count circuit is operable to provide the output side error count
external to the data processing circuit;
a data decoder circuit operable to apply a data decoding
algorithm to the detected output to yield a decoded output; and
a decoded output error count circuit operable to generate an
input side error count that is a number of errors remaining in the
decoded output, wherein the decoded output error count circuit is
operable to provide the input side error count external to the data
processing circuit.
Rejections on Appeal
Claims 1-6 and 20 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Yang (United States Patent Application Publication
Number 2010/0268996 Al; published October 21, 2010), Yamazaki (United
States Patent Application Publication Number 2004/0228021 Al; published
November 18, 2004) and Gueguen (United States Patent Application
Publication Number 2001/0010089 Al; published July 26, 2001). Final
Rejection 3-12.
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Appeal2014-007345
Application 13/483,100
Claims 7 and 8 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Yang, Yamazaki, Gueguen and Zhong ("Quasi-Cyclic
LDPC Codes for the Magnetic Recording Channel: Code Design and VLSI
Implementation," IEEE 2007). Final Rejection 13-14.
Claims 9-10 and 12-18 stand rejected under 35 U.S.C. §103(a) as
being unpatentable over Yang, Yamazaki, Gueguen and Ibing (United States
Patent Application Publication Number 2012/0020402 Al; published
January 26, 2016). Final Rejection 14-24.
Claims 11and19 stand rejected under 35 U.S.C. §103(a) as being
unpatentable over Yang, Yamazaki, Gueguen, Ibing and Ashikhmin (United
States Patent Application Publication Number 2005/0210367 Al; published
September 22, 2005). Final Rejection 24-25.
ANALYSIS
Rather than reiterate the arguments of Appellants and the Examiner,
we refer to the Appeal Brief (filed February 11, 2014 ), the Answer (mailed
April 17, 2014) and the Final Rejection (mailed October 9, 2013) for the
respective details. We have considered in this decision only those
arguments Appellants actually raised in the Brief.
We have reviewed the Examiner's rejections in light of Appellants'
arguments that the Examiner has erred. We disagree with Appellants'
conclusions. We adopt as our own (1) the findings and reasons set forth by
the Examiner in the action from which this appeal is taken and (2) the
reasons set forth by the Examiner in the Examiner's Answer in response to
Appellants' Appeal Brief, and concur with the conclusions reached by the
Examiner. We highlight the following for emphasis.
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Appeal2014-007345
Application 13/483,100
Appellants contend that "the examiner correctly admitted that neither
Yang nor Yamazaki disclose, teach or suggest the decoded output error
count circuit of claim 1." Appeal Brief 9 (citing Final Rejection, page 2).
Appellants contend the Examiner's findings that Guegen addresses the
deficiency of the Yang/Yamazaki combination is erroneous because
Gueguen discloses that the quality parameter is calculated, and "[ o ]ne of
ordinary skill in the art would not understand that such a 'calculated'
parameter implies or suggests the decoded output error count circuit of claim
1." Appeal Brief 10. Appellants further argue "not only does Gueguen not
disclose the decoded output error count circuit of claim 1, the output of the
calculation circuit is not the number of errors remaining as set forth in claim
1, but rather a statistical probability specifically used to create an
advantage." Appeal Brief 10. Appellants conclude, "[t]o argue that
Gueguen actually discloses use of a counter rather than calculation based on
statistical quantities effectively re-writes Gueguen to remove the advantages
specifically set forth in Gueguen." Id.
We do not find Appellants' arguments persuasive. Claim 1 requires a
detected output error count circuit that is operable to generate output side
error count or data. The Examiner finds that Yamazaki discloses a detected
output error count circuit not Gueguen. Final Rejection 5. The Examiner
relies upon Gueguen to teach the type of error count or data that can be
tabulated by a circuit. Final Rejection 5. We sustain the Examiner's
obviousness rejection of claim 1 because "the test [for obviousness] is what
the cmnbined teachings of the references would have suggested to those of
ordinary skill in the art." See In re Keller, 642 F.2d 413, 425 (CCPA 1981).
Appellants further argue that claim 12 was improperly rejected because the
Y ang/Y amazaki/Guegen combination failed to disclose the decoded output
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Appeal2014-007345
Application 13/483,100
error circuit. Appeal Brief 12. However, we do not find the combination
deficient as discussed above. Therefore, we sustain the Examiner's
obviousness rejection of claim 12, as well as the obviousness rejection of
claims 2-11 and 13-20 not separately argued. See Appeal Brief 12.
DECISION
The Examiner's obviousness rejections of claims 1-20 are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv). See 37
C.F.R. § 41.50(±).
AFFIRMED
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