Ex Parte Zettler et alDownload PDFPatent Trial and Appeal BoardNov 22, 201713472569 (P.T.A.B. Nov. 22, 2017) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/472,569 05/16/2012 Thomas Zettler INTP377EPUS 1709 18052 7590 Eschweiler & Potashnik, LLC Rosetta Center 629 Euclid Ave., Suite 1000 Cleveland, OH 44114 EXAMINER CHERY, MARDOCHEE ART UNIT PAPER NUMBER 2133 NOTIFICATION DATE DELIVERY MODE 11/27/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docketing @ eschweilerlaw. com inteldocs_docketing @ cpaglobal. com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte THOMAS ZETTLER, GUNTHER FENZL, OLAF WACHENDORF, RAIMAR THUDT, and RITESH BANERJEE1 Appeal 2017-007601 Application 13/472,569 Technology Center 2100 Before DEBRA K. STEPHENS, DANIEL J. GALLIGAN, and DAVID J. CUTITTA II, Administrative Patent Judges. CUTITTA, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of claims 1-23, which are all of the claims pending in the application. We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM. 1 According to Appellants, the real party in interest is Lantiq Beteiligungs- GmbH & Co. KG. See Appeal Br. 1. Appeal 2017-007601 Application 13/472,569 STATEMENT OF THE CASE According to Appellants, the claims are directed to a stream cache which splits the headers and bodies of incoming data packets. Abstract; Spec, ^ 35.2 Additionally, metadata is extracted from the incoming data packets and provided to a processor through an ingress queue. Spec. ^ 52. Claim 1, reproduced below, is representative of the claimed subject matter: 1. A system, comprising: a stream cache and a storage, wherein the stream cache includes: a stream cache controller adapted to control transmission of input data through the stream cache; and a stream cache memory, the stream cache memory being adapted: to store at least data packet headers of the input data, as determined by the stream cache controller, and to further output the stored data packet headers of the input data to a processor; and wherein the storage is adapted: to receive and store data packet bodies of the input data, as determined by the stream cache controller, and to further transmit the stored data packet bodies of the input data for output, wherein the system further includes an ingress queue unit apart from the processor that extracts metadata from the input data and to provide the metadata to the processor via a path excluding the stream cache memory and the storage. 2 This Decision refers to: (1) Appellants’ Specification filed May 16, 2012 (Spec.); (2) the Final Office Action (Final Act.) mailed March 31, 2016; (3) the Appeal Brief (App. Br.) filed October 12, 2016; (4) the Examiner’s Answer (Ans.) mailed April 6, 2017; and (5) the Reply Brief (Reply Br.) filed April 24, 2017. 2 Appeal 2017-007601 Application 13/472,569 REFERENCES AND REJECTION Claims 1-23 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Batra (US 2005/0246501 Al; published Nov. 3, 2005), McBride (US 2003/0103526 Al; published June 5, 2003), Kesavan (US 2007/0153796 Al; published July 5, 2007), and Rozario (US 7,352,748 Bl; issued Apr. 1,2008). Final Act. 3-19. Our review in this appeal is limited only to the above rejections and the issues raised by Appellants. Arguments not made are waived. See MPEP § 1205.02; 37 C.F.R. §§ 41.37(c)(l)(iv) and 41.39(a)(1). ISSUES 1. Does the Examiner err in finding the combination of Kesavan and Rozario teaches “wherein the system further includes an ingress queue unit apart from the processor that extracts metadata from the input data and to provide the metadata to the processor via a path excluding the stream cache memory and the storage,” as recited in claim 1 and similarly recited in claim 20? 2. Does the Examiner improperly combine Batra and McBride? CONTENTIONS AND ANALYSIS We disagree with Appellants’ contentions and, insofar as they relate to issues raised in this appeal, adopt as our own: (1) the findings and reasons set forth by the Examiner in the action from which this appeal is taken; and (2) the reasons set forth by the Examiner in the Answer in response to the Appeal Brief. With respect to the claims argued by Appellants, we highlight and address specific findings and arguments for emphasis as follows. 3 Appeal 2017-007601 Application 13/472,569 Issue 1 Appellants contend the Examiner erred in finding the combination of Kesavan and Rozario teaches “wherein the system further includes an ingress queue unit apart from the processor that extracts metadata from the input data and to provide the metadata to the processor via a path excluding the stream cache memory and the storage,” as recited in claim 1 and similarly recited in claim 20. App. Br. 5-7; Reply Br. 4-5. Specifically, Appellants argue that Kesavan teaches “a packet receiver 120 that extracts metadata from packets” but that those “receiver units 120, 320 are not an ingress queue unit.” App. Br. 6 (emphasis omitted). Appellants further argue Rozario teaches an “ingress memory 208,” but, according to Appellants, “the ingress memory 208 only holds data and provides no extraction of metadata therefrom as claimed.” App. Br. 6 (emphasis omitted); Reply Br. 4. We are not persuaded. The Examiner finds (Final Act. 6), and we agree, Kesavan teaches a packet “receiver 120 may extract/derive the metadata from [received] packets” (Kesavan 16, Fig. 3). The Examiner further finds, and we agree, Rosario teaches that “ingress memory 208 is separate from controller 406.” Final Act. 6 (citing Rosario Fig. 4). The Examiner combines Kesavan and Rozario such that extracted “metadata is provided to the processor via a path excluding the stream cache memory and storage.” Id. at 2-3. Appellants’ arguments improperly attack Kesavan and Rozario individually when the rejection is based on the combination of Kesavan and Rozario. In re Keller, 642 F.2d413, 426 (CCPA 1981). Specifically, Appellants’ argument that Kesavan does not teach an ingress queue unit 4 Appeal 2017-007601 Application 13/472,569 (App. Br. 6) does not address the Examiner’s finding that Rozario teaches an ingress queue unit, i.e., ingress memory 208 (Final Act. 7 (citing Rosario Fig. 4)). Further, Appellants’ argument that Rozario’s ingress memory does not extract metadata (App. Br. 6; Reply Br. 4) does not address the Examiner’s finding that Kesavan teaches a receiver, namely receiver 320, which extracts metadata (Final Act. 6 (citing Kesavan]} 16, Fig. 3)). Moreover, Appellants’ argument does not persuade us the Examiner’s combination of Kesavan, teaching extraction of metadata, and Rozario, teaching an ingress memory separate from a processor, would not result in “an ingress queue unit apart from the processor that extracts metadata from the input data and to provide the metadata to the processor via a path excluding the stream cache memory and the storage.”3 Id. at 2-3. 3 Claim 1 recites “an ingress queue unit apart from the processor that extracts metadata.” We first note that the claim potentially encompasses two different interpretations: 1) the ingress queue unit extracts metadata and 2) the processor extracts metadata. Appellants’ arguments are based on the first interpretation. See App. Br. 6. However, we also note that Appellants’ Summary of Claimed Subject Matter, citing Figures 2a-2c and paragraphs 52-53 of the Specification {id. at 2-3), does not disclose that the ingress queue unit extracts metadata. Instead, those portions of the Specification teach an ingress control block (ICTRF), rather than an ingress queue unit, extracts metadata. Spec. ]fl| 52-53 (“the processing engine (e.g., PROC 214).. . [is] shown receiving metadata (descriptor) 213 extracted by ICTRF 205 via an ingress queue unit 215.”). Nor do we readily find where the Specification teaches an ingress queue unit which extracts metadata. In the event of further prosecution, the Examiner may wish to review claim 1 and claim 20, which recites similar limitations as claim 1, for compliance with the written description requirement of 35 U.S.C. § 112, first paragraph and the definiteness requirement of 35 U.S.C. § 112, second paragraph. 5 Appeal 2017-007601 Application 13/472,569 Accordingly, we are not persuaded the Examiner fails to show the combination of Batra, McBride, Kesavan and Rozario teaches or suggests the limitations as recited in claim 1 and similarly recited in claim 20. Issue 2 Appellants contend the Examiner improperly combined Batra and McBride. App. Br. 3-5; Reply Br. 3—4. Specifically, Appellants argue Batra would be rendered “unsatisfactory for its intended purpose” because “in order [for the combination] to be operable, Batra . . . would need an additional, complex data organization and management system that would unduly increase the complexity and reduce the speed of [its] cache system.” App. Br. 5; see Reply Br. 3. Appellants further argue “one of ordinary skill would not be motivated to make the proffered modification based upon the negative teaching of McBride” (Reply Br. 4), specifically, that “data transfers with respect to the headers and header modification result in excessive traffic” (App. Br. 4 (citing McBride ^ 10)). We are not persuaded. The Examiner finds, and we agree, Batra teaches “caching techniques to maintain a local store of the most frequently used data,” i.e., “a selective caching technique.” Final Act. 4 (citing Batra Fig. 2, 17, 23); see Batra 30-31. The Examiner further finds (Final Act. 5), and we agree, McBride teaches “a packet comprises] a packet header 122 and body 124,” a “local processing element 150 stores the header data 122 in its cache 140 from local memory 120 for examination and/or modification,” and the packet’s “body 124 may be sent to the next processing element’s memory subsystem 180” (McBride ^ 8; see McBride 32, Figs. 1, 4). The Examiner combines Batra and McBride to teach that a 6 Appeal 2017-007601 Application 13/472,569 packet’s “header and body [are] processed separately, which frees up space in a cache when, for instance, only the header data is needed for a particular calculation.” Final Act. 5; Ans. 22. Appellants’ argument that the combination of Batra and McBride would “increase the complexity and reduce the speed of [Batra’s] cache system” does not persuade us that Batra would be rendered “unsatisfactory for its intended purpose.” App. Br. 4-5; Reply Br. 3. Appellants describe Batra as “directed to a system for performing selective caching . . . employ [ing] a technique to use the limited size of the cache most effectively” such that Batra “only cache[s] data from a pipe that exceeds some minimum capacity threshold.” App. Br. 4 (citing Batra ^ 19, 22-23). Initially, it is unclear whether Appellants proffer this description as Batra’s intended purpose; thus, Appellants have not identified what intended purpose, if any, is being frustrated by the combination. Assuming that Appellants are suggesting Batra’s intended purpose is selective caching (see id.), the deficiency in McBride’s system that Appellants proffer, “increasing] the complexity and reducing] the speed of the cache system” (id. at 5), does not persuasively explain how selective caching in Batra, would be inoperable or frustrated. Even assuming McBride’s packet header and body separation increased complexity or reduced the speed of selective caching, the overall selective caching operation is preserved. See In re Mouttet, 686 F.3d 1322, 1332 (Fed. Cir. 2012). A given course of action often has simultaneous advantages and disadvantages, and this does not necessarily obviate motivation to combine. Medichem, S.A. v. Rolabo, S.L., 437 F.3d 1157, 1165 (Fed. Cir. 2006). 7 Appeal 2017-007601 Application 13/472,569 Furthermore, we are not persuaded that separating packet headers and packet bodies for respective processing would necessarily reduce the speed and complexity of selective caching. Appellants rely on paragraph 10 of McBride for the proposition that “data transfers with respect to the headers and header modification results in excessive traffic.” App. Br. 4; Reply Br. 3—4. But that paragraph does not state that separating headers and bodies for respective processing is necessarily the cause of excessive traffic. Rather, that paragraph teaches decreasing traffic by “eliminating redundant or unnecessary memory accesses.” McBride ^ 10. Indeed, McBride’s elimination of “redundant or unnecessary memory accesses” {id.) includes separating packet headers and packet bodies for respective processing {id. Fig. 4, ^ 29 (a “preferred embodiment” includes “header examination and manipulation”), 32-33 (“packet body 412 may ... be sent to the memory subsystem 422, 432, of the next processing element 354 ... On path 45, the [packet] header 410 is accessed and manipulated by the local processing element 352.”)). To the extent Appellants argue McBride teaches away from the combination, i.e., “constitutes a negative teaching” (App. Br. 4), we are not persuaded because to teach away, a reference must “criticize, discredit, or otherwise discourage” investigation into the claimed solution. In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004). Appellants have not identified where McBride criticizes, discredits, or otherwise discourages processing separate packet headers and bodies in a selective caching system. Accordingly, we are not persuaded the Examiner improperly combined Batra and McBride. 8 Appeal 2017-007601 Application 13/472,569 We, therefore, sustain the 35 U.S.C. § 103(a) rejection of independent claims 1 and 20, as well as dependent claims 2-19 and 21-23, which are not argued separately. See App. Br. 5; 37 C.F.R. § 41.37(c)(l)(iv). DECISION For the reasons above, we affirm the Examiner’s decision rejecting claims 1-23. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 41.50(f). AFFIRMED 9 Copy with citationCopy as parenthetical citation