Ex Parte Zerbe et al

Patent Trial and Appeal Board

Jun 27, 2016

13452513 (P.T.A.B. Jun. 27, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/452,513 04/20/2012 Jared L. Zerbe
44429 7590 06/29/2016
Peninsula Patent Group (Rambus)
203 Woodrow Ave.
Santa Cruz, CA 95060
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
RBS2.Pl34C3 5797
EXAMINER
AGHDAM, FRESHTEH N
ART UNIT PAPER NUMBER
2632
NOTIFICATION DATE DELIVERY MODE
06/29/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
lkreisman@peninsulaiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JARED L. ZERBE, FRED F. CHEN, ANDREW HO,
RAMIN FARJAD-RAD, JOHN W. POULTON,
KEVIN S. DONNELLY, and BRIAN LEIBOWITZ
Appeal2014-009312
Application 13/452,513 1
Technology Center 2600
Before ELENI MANTIS MERCADER, JAMES W. DEJMEK, and
JOHN D. HAMANN, Administrative Patent Judges.
HAMANN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants file this appeal under 35 U.S.C. § 134(a) from the
Examiner's Final Rejection of claims 1, 6-8, and 33. The Examiner allowed
claims 9-32 and objected to claims 2-5. We have jurisdiction under
35 U.S.C. § 6(b). We reverse.
THE CLAIMED INVENTION
Appellants' claimed invention relates to "high speed electronic
signaling within and between integrated circuit devices." Spec. i-f 2.
1 According to Appellants, the real party in interest is Rambus, Inc. App. Br.
3.
Appeal2014-009312
Application 13/452,513
Claim 1 is illustrative of the subject matter of the appeal and is
reproduced below with emphasis added to highlight the dispositive disputed
limitation.
1. A first integrated circuit, comprising:
a transmitter having a transmit equalizer operable to
equalize first data to be transmitted to a second integrated
circuit; and
a receiver having a receive equalizer operable to equalize
second data to be received from the second integrated circuit;
where the first integrated circuit is operable to implement
at least two different modes, including
a first mode, in which the transmit equalizer and
the receive equalizer are each operable to mitigate
intersymbol interference arising from respective,
different symbol latencies relative to a main bit of the
first data and a main bit of the second data, respectively,
and
a second mode, in which a specific symbol latency
addressed by the receive equalizer in the first mode is not
addressed by the receive equalizer relative to the main bit
of the second data, and in \'l1hich the transmit equalizer is
configured to address intersymbol interference arising
from a symbol of latency relative to the main bit of the
first data which matches the specific symbol latency.
REJECTIONS ON APPEAL
(1) The Examiner rejected claims 1 and 33 under 35 U.S.C.
§ 103(a) as being unpatentable over the combination of Verbin et al. (US
2003/0223505 Al; Dec. 4, 2003) (hereinafter "Verbin") and Jared L. Zerbe
et al., Equalization and Clock Recovery for a 2.5-10-Gb/s 2-PAM/4-PAM
Backplane Transceiver cell, 38 IEEE J. SOLID-STATE CIR. 2121 (Dec. 2003)
(hereinafter "Zerbe"), collectively referred to as the "combination."
(2) The Examiner rejected claims 6 and 7 under 35 U.S.C. § 103(a)
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Appeal2014-009312
Application 13/452,513
as being unpatentable over the combination of Verbin, Zerbe, and
Mannering et al. (US 6,137,839; Oct. 24, 2000) (hereinafter "Mannering").
(3) The Examiner rejected claim 8 under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Verb in, Zerbe, and Lapointe et
al. (US 2008/0260016 Al; Oct. 23, 2008) (hereinafter "Lapointe").
DISPOSITIVE ISSUE ON APPEAL
For this appeal, the dispositive issue is whether the Examiner erred in
finding the combination teaches or suggests "a first mode ... operable to
mitigate intersymbol interference arising from ... different symbol
latencies relative to a main bit of the first data," as recited in claim 1 and
similarly recited in claim 33.
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
contentions that the Examiner erred. We find Appellants' arguments with
respect to the dispositive issue persuasive.
Appellants argue the combination, and Verbin in particular, fails to
teach or suggest, inter alia, a mode operable to mitigate intersymbol
interference ("ISI") arising from different symbol latencies relative to a main
bit of a first data stream. See App. Br. 12-13; Reply Br. 4--5. According to
Appellants, Verbin instead teaches equalization of "encoded data in the form
of multi-bit symbols, where each bit has no relative latency to a main bit.
Thus, ... there is no concept of ISI arising from different symbol 'latencies'
in terms of a 'main bit' as claimed in claim 1." See App. Br. 9-10 (citing
Verbin Figs. 1, 2A), 12-13; see also Reply Br. 5 (stating because "the
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Appeal2014-009312
Application 13/452,513
modulation causes the six-bit sequence to become a single entity, any notion
of a 'main bit' in the encoded six-bit sequence is nonexistent until ...
decoded, at the receiver. Thus, the equalization that is applied is done to the
entire symbol, which is ... different than the individual unencoded bits.").
Appellants also argue one of ordinary skill in the art would understand the
recitation of "relative to a main bit," as in claim 1, to require per-bit
equalization. See Reply Br. 5.
The Examiner finds "V erbin discloses that the equalization is carried
out on a per symbol basis, which in tum is carried out to every bit in the
symbol." Ans. 3; see also Final Act. 2-3 (citing Verbin i-fi-13, 204). The
Examiner concludes because "the equalization is carried out to all bits in the
symbol, the ISI arising from symbol latencies relative to any single bit in the
symbol is also mitigated." Id. The Examiner applies this same reasoning to
find "claim 1 does not require that the equalization is carried out on a per bit
basis[, because] ... the ISI arising from symbol latencies relative to any
single bit in the symbol is mitigated, the claimed limitation is implicitly met
.... " Ans. 3.
We agree with Appellants that one of ordinary skill in the art would
understand claim 1 's recitations of "relative to a main bit" in the context of
claim 1 to require per-bit equalization. Furthermore, we agree with
Appellants that equalization carried out on a per-symbol basis (an encoded
point in a constellation) differs substantively from a per-bit (unencoded bit
stream of data) basis. See Verbin Figs. 1, 2A; see also Reply Br. 4 ("Verbin
encodes, or modulates his data bit stream, as seen by encoder 22. Each
sequence of six bits is then 'encoded' or modulated into a symbol
represented by ONE point in the constellation of FIG. 2A."). Accordingly,
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Application 13/452,513
we agree the cited portions of the combination fail to teach or suggest a
mode operable to mitigate intersymbol interference ("ISI") arising from
different symbol latencies relative to a main bit of a first datastream. Thus,
we do not sustain the Examiner's rejection of claim 1.
CONCLUSION
Our above findings and reasoning also apply to claim 33, which
includes a similar limitation as the disputed limitation, as well as claims 6-8,
which depend from claim 1 and incorporate the disputed limitation.
DECISION
We reverse the Examiner's 35 U.S.C. § 103(a) rejection of claims 1,
6-8, and 33.
REVERSED
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