Ex Parte Yu et al

Patent Trial and Appeal Board

Jan 27, 2014

10197747 (P.T.A.B. Jan. 27, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/197,747 07/17/2002 James Yu RSTN-023 7846
96916 7590 01/27/2014
Wilson Ham & Holman
1811 Santa Rita Road, Ste. 130
Pleasanton, CA 94566
EXAMINER
O CONNOR, BRIAN T
ART UNIT PAPER NUMBER
2475
MAIL DATE DELIVERY MODE
01/27/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte JAMES YU and MIKE MORRISON
____________

Appeal 2011-007942
Application 10/197,747
Technology Center 2400
____________

Before GLENN J. PERRY, BRIAN J. McNAMARA and
JAMES B. ARPIN, Administrative Patent Judges.

GLENN J. PERRY, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b). We
affirm-in-part.
I. BACKGROUND
Appellants’ disclosed invention relates to classifying traffic at a
network node. Multiple on-chip memory arrays are programmed with
identical search entries, receive multiple packets, and distribute
classification searches related to the packets among the multiple on-chip
memory arrays. Abstract; Summary.
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Application Figure 12, reproduced below, is helpful in understanding
the invention.

Application Figure 12

Application Figure 12 illustrates a search distribution technique.
Multiple, content addressable memory (“CAM”) arrays (e.g., CAM array A
and CAM array B) are programmed with identical search entries and
classification searches related to incoming packets which are distributed
among the multiple CAM arrays. In Application Figure 12, incoming
packets 0-3 are searched in parallel.
The Examiner made the following rejections:
1. Claims 1, 2, 5-7, 10, 11, 13, 15, 17, 19, and 20 are rejected under
35 U.S.C. § 103(a) as unpatentable over Calvignac et al. (US 7,167,471 B2,
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Jan. 23, 2007; hereafter “Calvignac”) in view of Melvin (US 6,981,110 B1,
Dec. 27, 2005). Ans. 3.1
2. Claims 3, 4, 8, 9, 14, and 16 are rejected under 35 U.S.C. § 103(a)
as unpatentable over Calvignac in view of Davis (US 7,266,117 B1, Sep. 4,
2007). Ans. 7.
3. Claims 12 and 18 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Calvignac in view of Kejriwal et al. (US 6,757,249 B1,
Jun. 29, 2004; hereafter “Kejriwal”). Ans. 10.

II. DISCUSSION
Calvignac and Melvin
Appellants argue together as a group that claims 1, 2, 5-7, 10-11, 13,
15, 17, 19, and 20 are patentable over Calvignac and Melvin.
Claim 1 is reproduced below with disputed limitations emphasized.
1. A method of classifying traffic at a network node
comprising:
programming multiple on-chip memory arrays with
identical search entries, wherein the multiple on-chip memory
arrays are identically programmed with search entries of a first
on-chip memory array of the multiple on-chip memory arrays
identical to search entries of a second on-chip memory array of
the multiple on-chip memory arrays;
receiving multiple packets; and
distributing classification searches related to said packets
among said multiple programmed on-chip memory arrays
during simultaneous operation of all of said identically
programmed on-chip memory arrays.

1 Examiner’s Answer (“Ans.”) filed February 18, 2011.
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Appellants argue that the combination of Calvignac and Melvin does
not teach programming multiple on-chip memory arrays with identical
search entries. App. Br. 6.2 We disagree.
Calvignac Figure 2 is reproduced below.

Calvignac Figure 2.
Calvignac Figure 2 illustrates a packet processor including multiple
CAM pipelines (220A, 220B, 220C, 2200, 220E), as shown. Per Calvignac,
identical search entries are stored into each of these CAMs.

2 Appeal Brief (“App. Br.”) filed December 6, 2010.
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Each search key register 208 may comprise one or more
registers, e.g., pipeline registers 218A-B, organized in a
pipeline manner thereby enabling a search key to be assigned
to one or more tables based on a single thread number/table
number pair. An extra table number may be defined to
associate a search key with multiple tables, individually defined
by other numbers. Subsequently, a search key may be used to
index into two or more different tables, e.g., thereby improving
the utilization of the bandwidth. For example, a search key may
be stored in pipeline register 218A and assigned a particular
table number. In the next clock cycle, the search key in pipeline
register 218A may be transferred to CAM 211 as well as
transferring a duplicate of the same search key to pipeline
register 218B. The search key temporarily stored in pipeline
register 218B may then be assigned another particular table
number. Thus, a search key may be assigned to one or more
table numbers for a specific thread search action. The search
key temporarily stored in pipeline register 218B may be
transferred to CAM 211 in the next clock cycle.

Calvignac, 6:13-32 (emphases added). This passage explains how duplicate
search keys are stored in the various pipeline registers.
Appellants argue that the Examiner’s finding that the CAM pipelines
“‘must have identical search entries’” is based on faulty assumptions. App.
Br. 9. According to Appellants, the ability of the CAM pipelines to access
the same data within a single CAM device does not necessitate or justify the
Examiner’s finding of separate CAM devices with separate and identical
search entries. Id. Appellants provide a plausible alternative to their
interpretation of the Examiner’s understanding. Reply Br. 5-6.3 Appellants
proffer an example in which search duties are split based on portions of the
alphabet with separate CAM devices responsible for each section. Id.

3 Reply Brief (“Reply Br.”) filed April 18, 2011.
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However, the passage quoted above clearly discloses that pipeline
registers 218A-B are organized in a pipeline manner thereby enabling a
search key to be assigned to one or more tables based on a single thread
number/table number pair. Calvignac, 6:13-32. Thus, Calvignac
contemplates enabling a search key to be assigned to one or more tables and
specifically describes the use of a duplicate of the same search key to a
pipeline register. Id.
Appellants argue that Calvignac does not teach separate CAMs, as
recited in claim 1. Rather, Calvignac teaches a single CAM 211 with
multiple pipeline stages. App. Br. 7-8. We are not persuaded. It is true that,
as argued, Calvignac refers to a CAM with multiple pipeline stages, rather
than multiple CAMS. Claim 1, however, recites “memory arrays.” Each of
Calvignac’s pipeline stages functions as a recited “memory array.”
Appellants argue that Calvignac and Melvin do not teach
simultaneous operation of identically programmed, on-chip memory arrays.
App. Br. 9-10. In particular, Appellants argue that Melvin’s general
description of simultaneous packet processing is insufficient to teach
searches carried out simultaneously on identically programmed on-chip
memory arrays. Id. at 10. Appellants correctly note that the Examiner relies
on Melvin for teaching simultaneous packet operation over multiple
processors. Id. (quoting FOA 104).
The Examiner, however, relies on the combined teachings of
Calvignac and Melvin to teach or suggest the invention, as recited in claim
1. Melvin need not teach carrying out simultaneous searches on identically
programmed, on-chip memory arrays as long as there is stated sufficient

4 Final Office Action (“FOA”) dated June 4, 2010.
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rationale for combining the teachings of these two references. We determine
that there is. The Examiner noted that the search engine of Calvignac
processes a stream of packets. Ans. 14-15. Melvin’s technique is directed
to processing multiple packets. According to the Examiner, modifications to
Calvignac’s teachings to perform simultaneous operations, as taught by
Melvin, would produce an expected and successful method for processing
multiple packets. Id. We determine this rationale to be sufficient.
Appellants argue that, even though Melvin generally describes
simultaneous packet processing, the “general description” of simultaneous
packet processing is insufficient to teach the specific limitations related to
searches during simultaneous operation of identically programmed on-chip
memory arrays. App. Br. 10. We disagree. We are persuaded, instead, that
one of ordinary skill would have learned sufficiently from Melvin how to
adapt an arrangement, such as that taught by Calvignac, to simultaneously
process identically programmed on-chip memory arrays. See Ans. 14-16.
For the above reasons, we are not persuaded of error in the
Examiner’s rejection of claims 1, 2, 5-7, 10, 11, 13, 15, 17, 19, and 20 based
on the combined teachings of Calvignac and Melvin.

Calvignac and Davis
Appellants separately argue that Calvignac and Davis do not render
obvious claims 3, 4, 8, 9, 14 and 16. App. Br. 12. Appellants correctly note
that claims 3 and 4 depend from claim 1 and, therefore, require simultaneous
searching (third step of claim 1). Appellants also correctly note that claims
8 and 9 depend from claim 6 and, therefore, also require simultaneous
searching (claim 6). Further, Appellants correctly note that claim 14
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depends from claim 13 and that claim 16 depends from claim 15. As such,
these claims also require simultaneous searching (claim 15). App. Br. 12-
14.
The references cited in the Examiner’s rejection on appeal do not
include Melvin. See FOA 6. The Examiner’s Answer, however, misstates
the rejection as including Melvin. Ans. 15. Because the Examiner omitted
Melvin, Appellants are correct. The Examiner has not demonstrated how all
of the claim limitations are met by the combined teachings of Calvignac and
Davis alone. We, therefore, do not sustain the rejection of claims 3, 4, 8, 9,
14 and 16.

Calvignac and Kejriwal
Appellants separately argue that Calvignac and Davis do not render
obvious claims 12 and 18. App. Br. 14. Appellants correctly note that claim
12 depends from claim 6 and that claim 18 depends from claim 15. As such,
these claims also require simultaneous searching. Id. at 12-15.
The Examiner’s rejection does not include Melvin. See FOA 7. The
Examiner, however, misstates the rejection as including Melvin. Ans. 15.
Again, perhaps the Examiner intended to include Melvin in this rejection,
but did not do so. Because the Examiner also omitted Melvin from this
rejection, Appellants are correct. The Examiner has not demonstrated how
all of the claim limitations are met by the combined teachings of Calvignac
and Kejriwal alone. We, therefore, do not sustain the rejection of claims 12
and 18.
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III. CONCLUSION
We are not persuaded by Appellants’ arguments with respect to claims
1, 2, 5-7, 10, 11, 13, 15, 17, 19, and 20; and we sustain the rejection of these
claims. Because the Examiner has not made a prima facie case of
obviousness with respect to claims 3, 4, 8, 9, 12, 14, 16, and 18, we do not
sustain the rejections of those claims.
It is hereby ORDERED that the rejection of claims 1, 2, 5-7, 10, 11,
13, 15, 17, 19, and 20 is AFFIRMED.
It is further ORDERED that the rejection of claims 3, 4, 8, 9, 12, 14,
16, and 18 is REVERSED.

AFFIRMED-IN-PART

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