Ex Parte Yoo

Patent Trial and Appeal Board

Sep 28, 2012

11344630 (P.T.A.B. Sep. 28, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/344,630 02/01/2006 Chue San Yoo 2005.0002/1085.00337 7017
54657 7590 10/01/2012
DUANE MORRIS LLP (TSMC)
IP DEPARTMENT
30 SOUTH 17TH STREET
PHILADELPHIA, PA 19103-4196
EXAMINER
RUGGLES, JOHN S
ART UNIT PAPER NUMBER
1721
MAIL DATE DELIVERY MODE
10/01/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
________________

Ex parte CHUE SAN YOO
________________

Appeal 2011-002596
Application 11/344,630
Technology Center 1700
________________

Before HUBERT C. LORIN, LINDA M. GAUDETTE, and
MARK NAGUMO, Administrative Patent Judges.

NAGUMO, Administrative Patent Judge.

DECISION ON APPEAL

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Chue San Yoo (“Yoo”) timely appeals under 35 U.S.C. § 134(a) from
a final rejection1 of claims 1-12. We have jurisdiction under
35 U.S.C. § 6(b). We AFFIRM.
BACKGROUND
The subject matter on appeal relates to a photomask and a photomask
set.2
A photomask is typically a transparent plate of quartz or another
transparent material having a defined pattern, formed on the mask in chrome
or other opaque materials. (Spec. 4.) The pattern of interest in this appeal is
referred to as an “interconnect pattern,” and is comprised of lines, islands,
contact holes, or a combination of lines, islands, and contact holes. (Spec.
Figures 1-3.) The interconnect pattern provides lines of conductive material
that electrically connect laterally separated structures in the mask.
(Spec. 4.)3 The interconnect pattern also provides conductive material to

1 Office action mailed 23 December 2009.
2 Application 11/344,630, Universal Photomask and Set of Photomasks
Including a Universal Photomask, filed 1 February 2006. The specification
is referred to as the “630 Specification,” and is cited as “Spec.” The real
party in interest is listed as Taiwan Semiconductor Manufacturing Company,
Ltd. (Appeal Brief, filed 20 July 2010 (“Br.”), 2).
3 “An interconnect pattern is a pattern of interconnect leads – lines of
conductive material that electrically connect laterally separated features and
may be referred to as wires.”
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connect vertically between subjacent and superjacent layers of a multi-layer
device. (Spec. 4.)4
Photolithography can be compared to a high precision method of
making printed circuit boards (PCB). PCBs are used to mechanically
support and interconnect electrical components using conductive pathways,
tracks, or signal traces that can be photoetched on a thin metallic foil (e.g., a
copper sheet) that is laminated onto a non-conductive substrate (e.g., a
photographic plate). (Compare at col. 1, ll. 11-21.)5 The photoetching of
the foil can be accomplished by exposing the foil to light through a mask,
which is artwork of connecting leads, pads, and other conductive regions
required on the board. (Id.)
During the microfabrication of an integrated circuit, such as a
semiconductor device, typically a separate mask is used to form patterns in
successive layers on the device. (Spec. 5.) A typical semiconductor wafer
for an integrated circuit (comprising electronic components such as
transistors and capacitors) includes multiple layers formed on a substrate
with vertical interconnects. (Chang at 1, ¶¶ 0004, 0013.)6 For the physical
layout of a semiconductor device, a set of about 18 to 26 unique photomask

4 “Contacts and contact masks refer to contacts between device features at
different device levels and vias, in particular, provide contact between a
subjacent and superjacent metal layer. Throughout the specification,
contacts and vias will be referred to collectively as contacts.”
5 See infra note 10.
6 See infra note 12; see also US 2005/0110146A1, published 26 May 2005,
which is expressly incorporated by reference in the 630 Specification at 1.
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levels is typically required. (Hong at col. 1, ll. 33-38.)7 In a multiple layer
device, patterned conductive material on one level is electrically insulated
from patterned conductive material on another level by an insulating layer
made of dielectric material. (Chang at 1, ¶¶ 0004, 0013.)8 However, the
different layers may be vertically integrated and electrically interconnected
by structures referred to as vias. Id.
A photomask set is a plurality (e.g., 18 to 26) of masks, each having a
defined pattern. Photomasks and photomask sets are commonly used in
photolithography. (Spec. 4.) Photolithography is a process that transfers a
pattern from a photomask to a light-sensitive layer on a substrate. The
photomask set is fed into a photolithography instrument and the photomasks
are individually selected for exposure to create various structures on the
substrate.
STATEMENT OF THE CASE
The claimed invention is drawn to (1) a “universal” interconnect
pattern mask; and (2) a photomask set comprising a plurality of masks,
including a mask having a universal pattern that is alignable between a first
and a second mask and between said second mask and a third mask. The
claimed photomask and photomask set are characterized by their utility in
the fabrication of a semiconductor device.

7 See infra note 11.
8 See infra note 12.
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The Examiner maintains the following grounds of rejection:9
A. Claims 1-6 and 10-12 stand rejected under 35 U.S.C. § 103(a)
in view of the combined teachings of Compare10 and Hong.11
B. Claims 7-9 stand rejected under 35 U.S.C. § 103(a) in view of
the combined teachings of Compare, Hong, Chang,12 and
Tripathi.13
In the Appeal Brief and the Reply Brief,14 Yoo argues the
patentability of claims 1-12 generally; i.e., without setting forth separate
reasons for patentability with respect to any one or more claims apart from
the others, including separately rejected claims 7-9. Accordingly, the claims
stand or fall with claim 1. 37 C.F.R. § 41.37(c)(1)(vii) (2011).
Representative claim 1 reads:
1. A universal interconnect pattern mask usable to form a pattern
at multiple levels in the fabrication of a semiconductor device
and comprising an interconnect pattern.
(Claims App., Br. 19 (emphasis added).)

9 Examiner’s Answer mailed 2 September 2010 (“Ans.”).
10 US 3,784,380; 8 January 1974 (Ans. 3-7).
11 US 6,496,058 B1; 17 December 2002 (Ans. 3-7).
12 US 2003/0044059 A1; 6 March 2003 (Ans. 3-8).
13 US 6,109,775; 29 August 2000 (Ans. 3-8).
14 Filed 20 July 2010 (“Reply Br.”).
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DISCUSSION
Representative claim 1 stands rejected under 35 U.S.C. § 103 by the
Examiner as unpatentable over the combined teachings of Compare and
Hong.
The Examiner relies on Compare to show that photomasks of the type
claimed are old and have been used in the fabrication of integrated circuits.
In particular, the Examiner finds that Compare teaches a method for
preparing a mask for photoetching a PCB. (Ans. 4.) Compare prepares two
secondary masks. (Col. 3, ll. 53-57.) One is comprised of the positive
image of all possible leads and plugs (see Fig. 6). The other is comprised of
the positive image of all possible pads (pads are circular areas on the PCB
where the integrated circuit units are received and connected, and where the
leads on opposed faces of the PCB are interconnected; see labels 3 in Fig. 1
and Fig. 9). (Id.) The Examiner finds that the secondary masks are
“common” and therefore “universal” for masking contacts on a plurality of
PCBs. (Ans. 4.)
The Examiner finds that the gate array mask set15 described by Hong
would have suggested a “photomask set [that] would reasonably include a

15 A gate array mask set is a multi-level device in which the first two-thirds
of the mask levels are common to all designs and only the final one-third of
the mask levels is specific to a particular integrated circuit design.
(Col. 1, ll. 57-67.) Hong explains that using a gate array is beneficial
because it reduces the wafer fabrication time because the first two-thirds of
the masks do not have to be uniquely designed and made for a particular
integrated circuit design. Rather, the first two-thirds of the mask levels will
serve as “common masks” and be ready for a customized processing of the
remaining one-third of the mask layers. (Col. 1, ll. 60-67.)
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universal interconnect pattern mask usable to form a pattern at multiple
levels in the fabrication of a semiconductor (IC) device having an
interconnect pattern.” (Ans. 7.) As such, the Examiner finds that it would
have been obvious to a person having ordinary skill in the art to combine the
teachings of Compare and Hong in order to arrive at a photomask set in
which a proportion of its masks have a common pattern (i.e., universal). The
Examiner argues that a person having ordinary skill in the art would have a
reasonable expectation of success in reducing the manufacturing time and
increasing the production efficiency as a result of such a combination in
view of the Hong disclosure. (Id.)
In sum, the Examiner argues that the prior art masks disclosed in
Compare, which have interconnect patterns, are “usable to form a pattern at
multiple levels in the fabrication of a semiconductor device” in light of
Hong. (Ans. 16.) Thus, in effect, the Examiner concludes that the claimed
invention is an obvious combination of known elements in the photomask
prior art.
In response, Yoo argues as if claim 1 were a process claim. For
example, “Appellants point out that each of independent claims 1 and 4 also
recites the feature that a single universal mask is used more than one time in
a sequence of processing operations used to form one device (emphasis in
original).” (Br. 12.)16

16 See also Br. 13 (“Not only does Compare fail to teach the use of one
mask multiple times to form corresponding patterns in multiple layers,
Compare even fails to teach using a single mask multiple times in the
formation of any device. . . . Compare does not disclose using one mask
multiple times (emphasis in original).”);
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Yoo argues further that “[i]t is not sufficient to simply search the prior
art for a mask that could be usable or alignable as in the recited claims
because virtually any contact mask in any semiconductor fabrication process
as may be found in any of countless references, could have a mask set
designed around it such that it is so ‘usable’ or ‘alignable’.” Yoo argues
that one of ordinary skill in the art would not have combined Compare with
Hong because nothing is gained by their combination. (Br. 16; Reply Br. 6.)
Specifically, “[s]ince neither references [sic] teaches a mask being usable
multiple times from a device, one of ordinary skill in the art could not
combine the references to teach the use of a mask multiple times in the
formation of a device.” (Br. 16.)
These arguments are legally erroneous. “It is well settled that the
recitation of a new intended use for an old product does not make a claim to
that old product patentable.” In re Schreiber, 128 F.3d 1473, 1477 (Fed. Cir.
1997); In re Hack, 245 F.2d 246, 248 (CCPA 1957) (“[T]he grant of a patent

Id. (“Compare does not disclose using one mask multiple times in the
formation of a device (emphasis in original).”);
Id. at 14 (“Compare itself does not teach the feature that a single
universal mask can be used more than one time to pattern multiple layers
that combine to form one semiconductor device (emphasis in original).”).
Reply Br. 7 (“Using one mask multiple times to form patterns in
multiple levels of a multiple-level device is clearly outside the ‘scope and
content’ of Compare (emphasis added).”);
Id. at 8 (“Further, there is no evidence that Compare contemplates
using the masks in a multi-level semiconductor device as in the claimed
invention (emphasis added).”).
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on a composition or machine cannot be predicated on a new use of that
machine or composition.”).
The claimed invention is a product; more specifically, an article of
manufacture that is a universal interconnect pattern mask comprising an
interconnect pattern.17 The limitations in claim 1 define the mask’s physical
structure and its components.
The claimed invention recites only one positive claim limitation: “an
interconnect pattern.” Because the term “pattern” is generic and it
encompasses an infinite number of possible combinations of interconnecting
leads, pads, and contact holes, it cannot be interpreted to define a discrete
structure or component of the claimed mask.
The phrase “usable to form a pattern at multiple levels in the
fabrication of a semiconductor device” in the preamble to claim 1 merely
recites a purpose or intended use of the invention.
Therefore, in order to anticipate or render obvious the invention of
claim 1, a prior art reference is required to describe a universal interconnect
pattern mask comprising an interconnect pattern that would be usable to
form a pattern at multiple levels in the fabrication of a semiconductor
device.
Indeed, Yoo acknowledges that “virtually any contact mask” could be
usable to form a pattern on one layer of a semiconductor device.
(Reply Br. 6.) Because claim 1 does not require structural features, other
than “an interconnect pattern,” we conclude that a prior art mask defining an

17 Product claims are directed to a “machine, manufacture, or composition
of matter.” 35 U.S.C. § 101.
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interconnecting pattern anticipates the claim irrespective of whether the
reference teaches or suggests its repeated use in a process of making a
semiconductor device. As a matter of claim drafting, the discoverer of a
new use of a known product must protect his discovery by means of process
claims and not product claims.
Yoo does not argue that the secondary masks described in Compare
cannot be used to form a pattern at multiple levels in the fabrication of a
semiconductor device. Instead, Yoo argues that “Compare does not teach or
suggest that the photomask in Fig. 9 is usable at multiple levels on an
individual PCB.” (Br. 11.) In other words, Yoo’s argument is articulated as
if the claimed invention were a process. Said argument is not sufficient to
rebut the Examiner’s conclusion that the combined teachings of Compare
and Hong would have suggested to a person having ordinary skill in the art
at the time of invention the claimed product.
CONCLUSION
We affirm the prior art rejections of claims 1-12.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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