Ex Parte Yi et al

Patent Trial and Appeal Board

Feb 27, 2017

12475916 (P.T.A.B. Feb. 27, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/475,916 06/01/2009 Haoran Yi 6150-21300 4425
35690 7590 03/01/2017
MEYERTONS, HOOD, KIVLIN, KOWERT & GOETZEL, P.C.
P.O. BOX 398
AUSTIN, TX 78767-0398
EXAMINER
BARTELS, CHRISTOPHER A.
ART UNIT PAPER NUMBER
2184
NOTIFICATION DATE DELIVERY MODE
03/01/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patent_docketing@intprop.com
ptomhkkg @ gmail .com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HAORAN YI, MARY E. FLETCHER,
ROBERT E. DYE, and ADAM L. BORDELON
Appeal 2014-000015
Application 12/475,916
Technology Center 2100
Before MICHAEL J. STRAUSS, SHARON FENICK, and
PHILLIP A. BENNETT, Administrative Patent Judges.
STRAUSS, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2014-000015
Application 12/475,916
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1—36, which constitute all the claims pending in
this application. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
THE INVENTION
The claims are directed to a loop parallelization analyzer for data flow
programs. Spec., Title. Claim 1, reproduced below, is illustrative of the
claimed subject matter:
1. A non-transitory computer accessible memory medium that
stores program instructions executable by a processor to:
store a data flow program, wherein the data flow program
comprises one or more iterative data flow program portions,
wherein each iterative data flow program portion comprises data
flow program code configured to execute repeatedly in an
iterative manner;
automatically analyze the data flow program, including
performing dependence analysis for each of the one or more
iterative data flow program portions, thereby determining
whether each of the one or more iterative data flow program
portions is parallelizable, wherein said performing dependence
analysis comprises determining whether output from a first
subset or iteration of data flow program code of the iterative data
flow program portion is required by a second subset or iteration
of the data flow program code of the iterative data flow program
portion; and
store an indication of each of the one or more iterative data
flow program portions that is parallelizable, wherein the
indications are useable to parallelize the data flow program.
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
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Appeal 2014-000015
Application 12/475,916
Esslinger et al. (“Esslinger”) US 5,852,449 Dec. 22, 1998
Subrahmanyam US 6,247,173 B1 June 12,2001
REJECTIONS
The Examiner made the following rejections:
Claims 1—6, 14—33, and 36 stand rejected under 35 U.S.C. § 102(b) as
being anticipated by Esslinger. Ans. 3—16.
Claims 7—13, 34, and 35 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Esslinger and Subrahmanyam. Ans. 16—24.
APPELLANTS’ CONTENTION1
Appellants contend Esslinger’s systems/processes are already
parallelized such that there is no disclosure of performing a dependence
analysis to determine whether an iterative data flow program portion is
parallelizable and, consequently no disclosure of “stor[ing] an indication of
each of the one or more iterative data flow program portions that is
parallelizable, wherein the indications are useable to parallelize the data flow
program, as recited in claim 1.” App. Br. 15 (emphasis omitted).
ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments the Examiner has erred in rejecting independent claims 1, 30, and
36 under 35 U.S.C. § 102(b) as being anticipated by Esslinger. We agree
with Appellants’ conclusions as to this rejection of the claims.
1 We note Appellants raise additional contentions of error but we do not
reach them as our resolution of this contention is dispositive of the appealed
rejections under 35 U.S.C. §§ 102(b) and 103(a).
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Appeal 2014-000015
Application 12/475,916
The Examiner finds Esslinger’s discrete event simulator automatically
analyzes event list steps 101—107 and “determine [s] whether each of the one
or more iterative data flow program portions ‘thread of execution’ is
parallelizable ‘switches execution context. . . and executes it until it
blocks.’” Ans. 4. Appellants argue “Esslinger’s program is already
parallelized, and so there is no need to indicate whether an interative [sic.,
iterative] code portion that has not yet been parallelized is, in fact,
parallelizable. Nor are any of the alleged ‘indications’ described as
indicating whether an iterative code portion is parallelizable.” App. Br. 16.
Esslinger discloses “[a] graphical, interactive debugger for a
computer-based discrete-event simulation model of systems having parallel
processes . . . .” Esslinger, Abstract (emphasis added.) Although Esslinger
may debug and provide an animated simulation model of a hierarchical
directed process including identification of blocked transactions, we find no
explicit disclosure in the portions of Esslinger cited by the Examiner of
storing an indication of a data flow program portion that is determined to be
parallelizable. Accordingly, we agree with Appellants that Esslinger does
not anticipate the independent claims. While we appreciate the Examiner’s
technical reasoning attempting to explain why the disputed parallelization
analysis is performed, even if we find the explanation persuasive, it goes
beyond what is described by Esslinger and is instead attributable to the
Examiner.
Therefore, based on a preponderance of the evidence, we agree with
Appellants that Esslinger’s disclosure falls short of disclosing instructions
executable by a processor to store an indication of an iterative data flow
program portion that is [determined to be] parallelizable. Accordingly, we
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Appeal 2014-000015
Application 12/475,916
do not sustain the rejection of independent claim 1 under 35 U.S.C. § 102(b)
as being anticipated by Esslinger nor, for the same reasons, do we sustain the
rejection of independent claims 30 and 36 which include commensurate
limitations to that of claim 1 or the rejection of dependent claims 2—6, 14—
29, and 31—33. Furthermore, we do not sustain the rejection of dependent
claims 7—13, 34, and 35 under 35 U.S.C. § 103(a) over Esslinger and
Subrahmanyam, as the Examiner’s applications of the Subrahmanyam
reference fails to cure the deficiency in the base rejection addressed supra.
DECISION
We reverse the Examiner’s decision to reject claims 1—36.
REVERSED
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