10774178 (P.T.A.B. Feb. 19, 2014)

Ex Parte Yeung et al

Patent Trial and Appeal BoardFeb 19, 2014

10774178 (P.T.A.B. Feb. 19, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 10/774,178 02/06/2004 Minerva M. Yeung 42P16115 7185 45209 7590 02/19/2014 Mission/BSTZ BLAKELY SOKOLOFF TAYLOR & ZAFMAN 1279 Oakmead Parkway Sunnyvale, CA 94085-4040 EXAMINER ARCOS, CAROLINE H ART UNIT PAPER NUMBER 2195 MAIL DATE DELIVERY MODE 02/19/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte MINERVA M. YEUNG and YEN-KUANG CHEN ____________ Appeal 2011-007033 Application 10/774,178 Technology Center 2100 ____________ Before JEFFREY T. SMITH, MAHSHID D. SAADAT, and ROBERT E. NAPPI, Administrative Patent Judges. SAADAT, Administrative Patent Judge. DECISION ON APPEAL Appeal 2011-007033 Application 10/774,178 2 Appellants appeal under 35 U.S.C. § 134(a) from the Final Rejection of claims 1-4, 7, 10-15, 19, 39, and 40.1 We have jurisdiction under 35 U.S.C. § 6(b). We reverse. STATEMENT OF THE CASE Exemplary Claim Claims 1 and 12 are exemplary and read as follows with the disputed limitation in italics: 1. A method, comprising: monitoring a state of a multi-threaded application running in a system and a buffer associated with the multi- threaded application, wherein each thread includes one or more activities to be executed by the system; determining availability of a processor to perform simultaneous multi-threading and the buffer; coordinating dispatch of threads of the multi-threaded application to increase execution overlap of activities executing in the system based, at least in part, on the availability of the buffer; dynamically adjusting one or more of the frequency or the voltage applied to the processor based, at least in part, on the availability of the buffer and the coordination of the dispatch of the threads; and dynamically adjusting the buffer size based, at least in part, on the adjusted voltage or frequency applied to the processor and the coordination of the dispatch of the threads. 12. The method of claim 11, wherein monitoring the buffer fullness levels includes comparing the buffer level with 1 Claims 5, 6, 8, 9, 16-18, 20-38, and 41-50 have been cancelled. Appeal 2011-007033 Application 10/774,178 3 predetermined buffer fullness levels, wherein the predetermined buffer fullness levels include a high level mark and a low level mark. The Examiner’s Rejections Claims 12, 13, and 19 stand rejected under 35 U.S.C. § 112, second paragraph (Ans. 5).2 Claims 1, 11-14, 19, and 39 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Zaccarin (US 2003/0115428 A1) and Cota- Robles (US 2011/0056456 A1). (Ans. 6-11). Claims 2-4, 15, and 40 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Zaccarin, Cota-Robles, and Kling (US 6,662,203 B1). (Ans. 11-13). Claim 7 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Zaccarin, Cota-Robles, and Myers (US 4,811,208). (Ans. 13-14). Claim 10 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Zaccarin, Cota-Robles, Myers, and Jain (US 2002/0188884 A1). (Ans. 14-15). ANALYSIS Rejection under 35 U.S.C. § 112, second paragraph The Examiner finds that the limitation “the buffer level” lacks antecedent basis (Ans. 5). Appellants contend that the language of claims 12 and 19, when considered as a whole, is such that one of ordinary skill in the 2 The 35 U.S.C. § 112, second paragraph, rejection of claims 1-4, 7, 10, 11, 14, 15, 39, and 40 has been withdrawn by the Examiner (Ans. 4). Appeal 2011-007033 Application 10/774,178 4 art could interpret the metes and bound of the claim (App. Br. 9). We agree with Appellants’ reasoning and rebuttal and note that the recitation of the term “buffer level” refers to a level of buffer relative to the high level and low level marks of the buffer fullness levels. Therefore, the claims are not indefinite because one of ordinary skill in the art could reasonably ascertain the scope of the claims. Rejection under 35 U.S.C. § 103 The Examiner relies on paragraphs 15, 17, and 19 of Zaccarin for disclosing the disputed claim step of “dynamically adjusting the buffer size based, at least in part, on the adjusted voltage or frequency applied to the processor and the coordination of the dispatch of the threads” (Ans. 7). In response to Appellants’ argument (App. Br. 10-11) that the buffer size in Zaccarin is always fixed, the Examiner points to paragraph 15 of Zaccarin for “adjusting processor clock speed (i.e. frequency) or voltage based on the monitored data buffer level which will result in adjusting data buffer level” (Ans. 16). The Examiner further takes the position that, in view of Appellants’ disclosure in paragraph 32 of their Specification, adjusting the buffer level is the same as adjusting the buffer size (Ans. 17). Appellants contend that, according to paragraph 27 of their Specification, [i]f a “level” of a buffer indicates an overflow condition (e.g., data size was too large to store in said buffer), the physical “size” of said buffer may be increased (i.e., so said data, which was too large to store previously, may be stored in the enlarged buffer). (Reply Br. 4). Appellants further explain that, contrary to the Examiner’s reading of paragraph 32 of their Specification (see Ans. 17), changing the Appeal 2011-007033 Application 10/774,178 5 buffer level merely indicates a change in the level of buffer fullness, and not the size of the buffer (Reply Br. 5). We agree with Appellants. We find that Zaccarin, at best, discloses changing the data flow based on the buffer level in buffer 32 (¶¶ [0014] – [0015]). However, the Examiner has not identified any teachings in Zaccarin related to the buffer size, much less dynamically changing a buffer size. In fact, as asserted by Appellants (App. Br. 10-11), paragraph 19 of Zaccarin indicates that “the variables B0, B1, B2 and B3 in both FIGS. 2 and 3 are represented as being static” and “[t]he overall buffer size of the buffer block 32 is similarly fixed.” CONCLUSIONS Based on the analysis above, we are persuaded by Appellants’ contentions that the Examiner has erred in rejecting claims 12, 13, and 19 as being indefinite and in rejecting claim 1 as being obviousness under 35 U.S.C. § 103(a). Therefore, we do not sustain the 35 U.S.C. § 112, second paragraph, rejection of claims 12, 13, and 19. Additionally, in view of the above discussion and the failure of the Examiner to point to any teachings in the other applied prior art references to overcome the deficiencies of Zaccarin, we do not sustain the rejection of claim 1, independent claims 14 and 39 reciting similar features related to dynamically changing the buffer size, or the remaining claims dependent thereon. Appeal 2011-007033 Application 10/774,178 6 DECISION The decision of the Examiner to reject claims 1-4, 7, 10-15, 19, 39, and 40 is reversed. REVERSED msc