Ex Parte Yasuda

Patent Trial and Appeal Board

Jan 26, 2018

14611223 (P.T.A.B. Jan. 26, 2018)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/611,223 01/31/2015 Takeo Yasuda JP920120016US3 9746
45992 7590 01/29/2018
IBM CORPORATION (JVM)
C/O LAW OFFICE OF JACK V. MUSGROVE
2911 BRIONA WOOD LANE
CEDAR PARK, TX 78613
EXAMINER
CALDWELL, ANDREW T
ART UNIT PAPER NUMBER
2182
MAIL DATE DELIVERY MODE
01/29/2018 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte TAKEO YASUDA
Appeal 2017-008004
Application 14/611,22s1
Technology Center 2100
Before CAROLYN D. THOMAS, JOSEPH P. LENTIVECH, and
MICHAEL J. ENGLE, Administrative Patent Judges.
ENGLE, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from a final rejection of
claims 7—16 and 18—22, which are all of the claims pending in the
application. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.
Technology
The application relates to “logic circuits for computational devices,
and more particularly to a barrel shifter or rotator.” Spec. 1:10-11.
In the simplest shifter circuit, each bit is incrementally shifted
one place at a time, so shifting data by n bits would require
n clock cycles. This delay is unacceptable for conventional
systems having, e.g., 64-bit or 128-bit data values, so an
1 According to Appellant, the real party in interest is International Business
Machines Corp. App. Br. 2.
Appeal 2017-008004
Application 14/611,223
improved design known as a barrel shifter has been devised
which can shift long-bit values in a single clock cycle.
Spec. 1:20-24.
Claim 7 is illustrative and reproduced below:
7. A circuit for encoding selection signals to control selectors of
a multi-stage barrel shifter, comprising:
a sign magnitude to 2’s complement converter having a
sign input which receives an input shift direction for a shift
operation and having a magnitude input which receives an input
shift amount for the shift operation, wherein said sign magnitude
to 2’s complement converter uses a 2’s complement of the input
shift amount to generate a first decoder signal for controlling a
first selector and to generate a second decoder signal for
controlling a second selector.
Rejections
Claims 7—16 and 19—22 stand rejected under 35 U.S.C. § 103(a) as
obvious over the combination of Applicant Admitted Prior Art (“AAPA”)
and Wikipedia (Signed Number Representations). Final Act. 2.
Claim 18 stands rejected under 35 U.S.C. § 103(a) as obvious over the
combination of AAPA, Wikipedia, and Chu (US 5,555,202). Final Act. 8.
ISSUES
Did the Examiner err in concluding the combination of AAPA and
Wikipedia renders obvious claim 7?
ANALYSIS
The Examiner determines:
AAPA does not teach a sign magnitude to 2’s complement
converter circuit.
However, Wikipedia explicitly teaches using 2’s
complement to represent sign magnitude values ....
2
Appeal 2017-008004
Application 14/611,223
Therefore, it would have been obvious to one of ordinary
skill in the art at the time of [the] invention to modify the invert
with shift right circuit (i.e. element 16 [in Spec. Fig. 1]) as taught
by AAPA by using 2’s complement... as taught by Wikipedia
in order to use a number representation system that eliminates
the need for multiple representations of zero, thus decreasing the
complexity of the function performed by element 16.
Final Act. 3^4; Ans. 2—3. The Examiner further explains:
Appellant and the instant application admit that the key inventive
concept here is using 2’s complement conversion at element 36
of FIG. 2 [of the Specification] rather than invert with shift right
at element 16 of FIG. 1. One of the purposes of the 2’s
complement number system is to eliminate multiple
representations of zeros.
Ans. 3.
Appellant argues the Examiner “never explains why multiple
representations of zero is related to control signals for decoding selectors of
a barrel shifter” (App. Br. 9) and “[m]ultiple representations of zero are not
part of Appellant’s invention and they are not part of any problem in the
prior art barrel shifting circuit (AAPA).” Reply Br. 4.
Given the record before us, we agree with Appellant that the
Examiner has not explained why multiple representations of zeros would
have been a problem for this particular control signal. For example, in
Figures 1 and 2 of the Specification, the input signals “shift_right” (a single
bit) and “shift_amount<0:5>” (six bits) can be considered a single 7-bit
number in “sign magnitude” format (i.e., with the sign being the shift
direction from “shift_right” and the magnitude being the number of bits to
shift from “shift_amount”). See Spec. 4:4—12, 2:11—13. A 7-bit number in
sign magnitude format can range from -63 to +63, with two representations
for 0 (specifically, 0000000 and 1000000). In 2’s complement format,
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Appeal 2017-008004
Application 14/611,223
however, a 7-bit number could range from -64 to +63, with only one
representation for 0 (specifically, 0000000). Thus, elimination of the second
zero theoretically permits one extra negative value in 2’s complement (i.e.,
-64). Yet because the input can only range as low as -63, any value output
from a 2’s complement converter likewise could only range as low as -63,
thereby never using the extra value -64 created by the elimination of the
second zero. Eliminating the extra zero therefore has no benefit for the
converter itself. Any benefit would have to arise from mathematical
operations after the converter, yet the Examiner has not explained
sufficiently whether and why a person of ordinary skill in the art would have
understood that the downstream MSB and LSB decoders and drivers
(labeled 22 and 24 in Figure 1) would have encountered any problems from
a second zero. For example, Appellant argues “[t]he output of the 2’s
complement converter circuit... is not even used as operand data,” so the
concept of having both a positive zero and a negative zero is not a problem.
App. Br. 9-10. The Examiner therefore has not adequately supported the
finding that elimination of a second zero would have motivated a person of
ordinary skill in the art to modify AAPA.2
2 We also note the Examiner may be confusing a converter with a negation
operation. See App. Br. 13; Ans. 3 & n.l. A converter has an input and
output in different formats, here converting sign magnitude format to 2’s
complement format, which requires inverting and adding one only if the
input is negative. In contrast, a negation operation would have an input and
output in the same format, which for 2’s complement requires always
inverting and adding one. Even if it were obvious to replace “the inversion
. . . function of element 16” with the 2’s complement negation operation
(both of which always invert), see Ans. 3, that does not necessarily render
obvious replacing an inverter with a 2’s complement converter (which
inverts only if the input is negative).
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Appeal 2017-008004
Application 14/611,223
Accordingly, we do not sustain the Examiner’s rejection of claims 7
16 and 18-22.
DECISION
For the reasons above, we reverse the Examiner’s decision rejecting
claims 7—16 and 18—22.
REVERSED
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