Ex Parte YAP et al

Patent Trial and Appeal Board

Jan 25, 2018

14086745 (P.T.A.B. Jan. 25, 2018)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/086,745 11/21/2013 WENG F. YAP MT12419ZK (038.0608) 1039
50996 7590 01/29/2018
NXP (FS) - LKGlobal
6501 William Cannon Drive West
Austin, TX 78735
EXAMINER
VU, DAVID
ART UNIT PAPER NUMBER
2818
NOTIFICATION DATE DELIVERY MODE
01/29/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip. department .u s @ nxp. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte WENG F. YAP, SCOTT M. HAYES, and ALAN J. MAGNUS
Appeal 2017-002073
Application 14/086,745
Technology Center 2800
Before KAREN M. HASTINGS, JAMES C. HOUSEL, and
JEFFREY R. SNAY, Administrative Patent Judges.
SNAY, Administrative Patent Judge.
DECISION ON APPEAL1
Appellants2 appeal under 35 U.S.C. § 134(a) from the Examiner’s
decision rejecting claims 1-3, 7, 8, 10, 15, and 20-27. We have jurisdiction
under 35 U.S.C. § 6(b).
We reverse.
1 We cite to the Specification (“Spec.”) filed November 21, 2013; Final
Office Action (“Final Act.”) dated November 19, 2015; Appellants’ Appeal
Brief (“App. Br.”) dated June 29, 2016; Examiner’s Answer (“Ans.”) dated
November 25, 2016; and Appellants’ Reply Brief (“Reply Br.”) dated
November 30, 2016.
2 Appellants identify Freescale Semiconductor, Inc. as the real party in
interest. App. Br. 2.
Appeal 2017-002073
Application 14/086,745
BACKGROUND
The invention relates to a method for fabricating an optically-masked
microelectronic package. Spec. 1. According to Appellants’
Specification, use of transparent dielectric material layers in a
microelectronic package undesirably permits a third party observer to obtain
critical information pertaining to the internal package architecture. Id. ^ 16.
Appellants’ described method provides a relatively opaque mask layer such
that internal architecture is concealed from external visual inspection. Id.
17-18. Claim 1 is reproduced below from the Claims Appendix of the
Amended Appeal Brief, with emphasis added to highlight the key recitation
in dispute:
1. A method for fabricating an optically-masked
microelectronic package, comprising:
building redistribution layers over the frontside of a
semiconductor die, the redistribution layers comprising a body
of dielectric material in which a plurality of interconnect lines
are formed;
forming an optical mask layer overlying the frontside of
the semiconductor die and at least a portion of the redistribution
layers, the optical mask layer having an opacity greater than the
opacity of the body of dielectric material and blocking or
obscuring visual observation of an interior portion of the
microelectronic package through the redistribution layers', and
producing a contact array before or after formation of the
optical mask layer electrically coupled to the plurality of
interconnect lines, at least some of the contacts included within
the contact array projecting through openings in the optical mask
layer, the openings sized such that a circumferential clearance
having a predetermined gap width is formed around each contact
projecting through the optical mask layer.
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Appeal 2017-002073
Application 14/086,745
Like claim 1, independent claim 24 requires, inter alia, an optical
mask that has an opacity greater than that of the underlying dielectric
redistribution layers. The remaining claims on appeal depend from claim 1
or 24.
REJECTIONS
I. Claims 1, 7, 8, 10, 15, and 203 stand rejected under 35 U.S.C. § 102 as
anticipated by Lin.4
II. Claims 21, 22, and 24-27 stand rejected under 35 U.S.C. § 103 as
unpatentable over Lin.
III. Claims 2 and 3 stand rejected under 35 U.S.C. § 103 as unpatentable
over Lin and Dunlap.5
OPINION
Rejection I
Relevant to Appellants’ main argument on appeal, the Examiner finds
that Lin describes a method for fabricating a microelectronic package that
includes providing a metal layer 32 and dielectric redistribution layers 48.
Pinal Act. 2 (citing Lin figure 8, ^ 21). The Examiner states that Lin’s
metal layer 32 “[has] an opacity greater than the opacity of the body of
dielectric material,” such that the metal layer is “blocking or obscuring
visual observation of an interior portion of the microelectronic package.” Id.
3 The Examiner withdraws this ground of rejection as applied to claims 9,
11, 12, and 16. Ans. 2.
4 US 2009/0140442 Al, published June 4, 2009 (“Lin”).
5 US 8,337,657 Bl, issued December 25, 2012 (“Dunlap”).
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Appeal 2017-002073
Application 14/086,745
Appellants argue that “the Examiner has not presented any argument
or evidence supporting the proposition” that Lin’s layer 32 necessarily has
an opacity greater than that of the dielectric layers. App. Br. 23. In response
to Appellants’ argument, the Examiner contends that “[a] 11 metal material
layers have a higher opacity than dielectric materials as would have been
well known.” Ans. 4.
On this appeal record, we are persuaded that the Examiner fails to
identify evidence sufficient to support a finding that Lin’s layer 32 exhibits
an opacity that is greater than that of the underlying dielectric layers. Nor
does the Examiner present any evidence to support a finding that Lin’s layer
32 performs the function of “blocking or obscuring visual observation of an
interior portion of the microelectronic package through the redistribution
layers,” as recited in Appellants’ claims.
Lin describes layer 32 as a passivation layer which is “chosen to have
good selectivity as a silicon etchant so it can act as an etch stop during later
removal of the dummy substrate.” Lin ^ 21. As materials suitable for use as
passivation layer 32, Lin identifies silicon nitride, silicon dioxide, silicon
oxynitride, other dielectric materials, or metal such as copper. Id. We are
not directed to, nor do we find, any disclosure in Lin regarding opacity of
layer 32, opacity of dielectric layers 48, or a desire to obscure visual
observation of an interior portion of the microelectronic package. To the
extent that the Examiner’s finding is one of inherency, it is improperly based
on a mere possibility or probability that Lin’s metal layer might be relatively
opaque and obscuring (see also Reply Br. 9, 10, discussing “the existence of
transparent metal films”). See Continental Can Co. USA v. Monsanto Co.,
948 L.2d 1264, 1269 (Led. Cir. 1991) (“Inherency . . . may not be
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Appeal 2017-002073
Application 14/086,745
established by probabilities or possibilities. The mere fact that a certain thing
may result from a given set of circumstances is not sufficient.”). For the
foregoing reasons, we are persuaded that the Examiner has not identified
evidence sufficient to support the anticipation finding.6
Accordingly, Rejection I is not sustained.
Rejections II and III
Each of Rejections II and III is premised on the same findings that Lin
discloses a metal layer having a greater opacity than the underlying
dielectric layers, and that the metal layer obscures visual observation of
interior portions of the microelectronic package. Final Act. 5-6. Because
the Examiner fails to identify evidence sufficient to support those findings,
Rejections II and III also are not sustained.
DECISION
The Examiner’s rejections of claims 1-3, 7, 8, 10, 15, and 20-27 are
reversed.
REVERSED
6 The Board relies on the involved parties to focus the issues and decides on
those issues based on facts and arguments presented by the involved parties.
See Ex Parte Frye, 293 F. 1013 (BPAI 2010 (precedential)).
5