Ex Parte Yang et alDownload PDFPatent Trial and Appeal BoardJun 25, 201813333256 (P.T.A.B. Jun. 25, 2018) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 13/333,256 12/21/2011 51472 7590 06/27/2018 GARLICK & MARKISON (BRCM) 106 E. 6th Street, Suite 900 AUSTIN, TX 78701 FIRST NAMED INVENTOR Zhijie Yang UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. BP23216 8218 EXAMINER MUNG,ONS ART UNIT PAPER NUMBER 2486 NOTIFICATION DATE DELIVERY MODE 06/27/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): MMURDOCK@TEXASPATENTS.COM bpierotti@texaspatents.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte ZHIJIE YANG and BHASKAR SHERIGAR MALA SHERIGAR Appeal2016-005665 Application 13/333,256 1 Technology Center 2400 Before BRADLEY W. BAUMEISTER, JASON J. CHUNG, and MICHAEL J. ENGLE, Administrative Patent Judges. CHUNG, Administrative Patent Judge. DECISION ON APPEAL This is a decision on appeal under 35 U.S.C. § 134(a) from the Final Rejection of claims 1-28. We have jurisdiction under 35 U.S.C. § 6(b ). We reverse. INVENTION The invention is directed to "performing video coding using blocks and/or sub-blocks in accordance with such digital video processing." Spec. 2:4--5. Claim 1 illustrates the invention: 1. An apparatus comprising: an input configured to receive a bitstream, corresponding to a video signal, and including a plurality of tree blocks; 1 Appellants list Broadcom Corp. as the real party in interest. App. Br. 2. Appeal2016-005665 Application 13/333,256 a parser and treeblock splitter configured to: partition adaptively the plurality of tree blocks (TBs) into a plurality of subtreeblocks (STBs) such that each of the plurality of TBs correspond[] to a respective plurality of STBs; and output the plurality of STBs, in parallel, via a first pathway and a second pathway of a plurality of pathways; a video decoder including: a first decoding engine configured to receive the plurality of STBs via the first pathway and to perform a first at least one video decoding operation to generate a first at least one intermediate decoded resultant; and a second decoding engine configured to receive the plurality of STBs via the second pathway and to perform a second at least one video decoding operation that is different than and is independent from the first at least one video decoding operation, in parallel with the first decoding engine performing the first at least one video decoding operation, to generate a second at least one intermediate decoded resultant; and a combiner configured to combine the first at least one intermediate decoded resultant and the second at least one intermediate decoded resultant to generate at least one decoded resultant; and wherein: the first decoding engine configured to partition adaptively the plurality of STBs further into a plurality of sub- STBs and to perform the first at least one video decoding operation on the plurality of sub-STBs to generate the first at least one intermediate decoded resultant; the parser and tree block splitter configured to partition adaptively the plurality of TBs into a plurality of STBs based on at least of at least one characteristic associated with at least one local processing condition of the apparatus and at least one characteristic associated with at least one source device to provide the bitstream via at least one communication network; and each of the plurality of STBs having a size of 32 pixels by 32 pixels. 2 Appeal2016-005665 Application 13/333,256 App. Br. 26-27 (emphases added) (Claims App'x). REJECTION AT ISSUE Claims 1-28 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Han et al. (US 2011/0096826 Al; published Apr. 28, 2011) (hereinafter, "Han") and Tsou et al. (US 2007/0292113 Al; published Dec. 20, 2007) (hereinafter, "Tsou"). Final Act. 3-12. ANALYSIS The Examiner finds paragraphs 23 5 and 317 of Han teach: output the plurality of STBs in parallel, via a first pathway and a second pathway of a plurality of pathways ... [and] a first decoding engine ... configured to receive the plurality of STBs via the first pathway ... [and] a second decoding engine ... configured to receive the plurality of STBs via the second pathway (hereinafter, "the disputed limitation") as recited in claims 1 and 6 (and similarly recited in claim 18). Final Act. 5---6, 10-11 (citing Han i-fi-1235, 317). In addition, the Examiner finds Han teaches "if there are a plurality of arithmetic processors, the arithmetic processors may continuously and simultaneously perform independent parsing and independent decoding on different data units." Ans. 3 (citing Han i1235) (emphasis added). The Examiner finds independent claims 1, 6, and 18 do not recite the "same" signals are processed using different respective video decoding operations. Ans. 6. Appellants argue Han's parallel processing fails to teach that a first decoding engine and a second decoding engine receive the same plurality of 3 Appeal2016-005665 Application 13/333,256 sub-treeblocks (hereinafter, "STBs"). App. Br. 16-25; Reply Br. 2--4. We agree with Appellants. Although the Examiner is correct that the independent claims do not recite the word "same" (Ans. 6), claim 1 recites "a first decoding engine configured to receive the plurality of STBs" and "a second decoding engine configured to receive the plurality of STBs." Here, "the plurality of STBs" received by both decoding engines share the same antecedent basis and therefore refer to the same plurality of STBs. We agree with the Examiner finding that Han teaches "if there are a plurality of arithmetic processors, the arithmetic processors may continuously and simultaneously perform independent parsing and independent decoding on different data units." Ans. 3 (citing Han i-f 235) (emphasis added). In addition, paragraph 317 of Han relied upon by the Examiner (Final Act. 5---6 (citing Han i-f 31 7)) also recites performing parallel decoding simultaneously on different coding units. Han i-f 317. Thus, Han's performing parallel decoding simultaneously on different coding units of an input signal (Han i-fi-1235, 317) fails to teach the disputed limitation. The Examiner fails to consider the independent claims as having the "same" "plurality of STBs" (Ans. 6); therefore, the Examiner did not respond sufficiently to Appellants' arguments (App. Br. 16-24; Reply Br. 2--4). Accordingly, we do not sustain the Examiner's rejection of: (1) independent claims 1, 6, and 18; and (2) dependent claims 2-5, 7-17, and 19-28 under 35 U.S.C. § 103(a). 4 Appeal2016-005665 Application 13/333,256 DECISION We reverse the Examiner's decision rejecting claims 1-28 under 35 U.S.C. § 103(a). REVERSED 5 Copy with citationCopy as parenthetical citation