Ex Parte Yang et al

Patent Trial and Appeal Board

Dec 8, 2017

13799955 (P.T.A.B. Dec. 8, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/799,955 03/13/2013 Bin Yang 122830/1173-075 1658
115309 7590 12/12/2017
W&T/Onalonmm
EXAMINER
106 Pinedale Springs Way
Cary, NC27511
BODNAR, JOHN A
ART UNIT PAPER NUMBER
2893
NOTIFICATION DATE DELIVERY MODE
12/12/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents @ wt-ip.com
us-docketing@qualcomm.com
ocpat_uspto@qualcomm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BIN YANG, XIA LI, and PR CHIDAMBARAM
(Applicant: QUALCOMM INC.)
Appeal 2017-004216
Application 13/799,955
Technology Center 2800
Before TERRY J. OWENS, N. WHITNEY WILSON,
DEBRA L. DENNETT, Administrative Patent Judges.
OWENS, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
The Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’
rejection of claims 1-13 and 25. We have jurisdiction under
35 U.S.C. § 6(b).
The Invention
The Appellants claim a metal oxide semiconductor device. Claims 1
and 13 are illustrative:
1. A metal oxide semiconductor (MOS) device comprising:
a first material having a first n-metal or p-metal work
function;
a first plurality of gates comprising the first material;
Appeal 2017-004216
Application 13/799,955
a second plurality of gates comprising the first material;
and
a dummy gate positioned between the first plurality of
gates and the second plurality of gates and the dummy gate
comprising a second material having a work function opposite
that of the first material, wherein the dummy gate is connected
to one of a Vss or a Vdd to fix a voltage level for the dummy
gate.
13. A metal oxide semiconductor (MOS) device comprising:
a first means for having a first n-metal or p-metal work
function;
a first gate means comprising a first plurality of gates
formed from the first means;
a second gate means comprising a second plurality of
gates formed from the first means; and
a dummy gate means positioned between the first gate
means and the second gate means and comprising a second
means for having a work function opposite that of the first
means.
Huang
The References
US 2011/0147765 A1 June 23,2011
Blatchford US 2012/0107729 A1 May 3, 2012
Anderson US 2012/0126336 A1 May 24, 2012
Holst US 2013/0049835 A1 Feb. 28, 2013
Yu US 2013/0187237 A1 July 25, 2013
The Rejection
(filed Jan. 23,2012)
The claims stand rejected under 35 U.S.C. § 103 as follows: claims 1-
5, 8, 9, 11-13, and 25 over Huang in view of Blatchford and Anderson,
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Application 13/799,955
claims 6 and 7 over Huang in view of Blatchford, Anderson and Holst, and
claim 10 over Yu in view of Huang, Blatchford and Anderson.1
OPINION
We reverse the rejections and, under 37 C.F.R. § 41.50(b), introduce a
new ground of rejection. Regarding the rejections we need address only the
independent claims (1 and 13).2
Huang discloses an MOS device comprising a dummy gate (330)
between and isolating adjacent/neighboring NMOSFET devices (302, 304),
each of which comprises a gate electrode (322) having an n-type work
function 23, 27; Fig. 3). The dummy gate (330) has a p-type work
function, opposite to that of the adjacent/neighboring NMOSFET devices’
gate electrodes (322), to “ensure that no leakage current occurs between
neighboring NMOSFET devices 302, 304” (]f 29).3
Blatchford states that “[a]s used herein, a neighboring dummy feature
is an extra printed feature that is positioned adjacent to an end active gate
that enables improved patterning particularly for the end active gate feature”
fl[ 7) and “can be subsequently removed after its printing, or remain on the
final IC in which case the neighboring dummy feature will be an electrically
isolated (i.e., unconnected) feature” (id.). Blatchford states that a “pitch
effect where the spacing [PI; Fig. 1] of the neighboring dummy gate level
1 The Examiner apparently inadvertently omits Anderson from the rejection
of claim 10 which depends from claim 1 (Final Act. 11).
2 The Examiner does not rely upon Holst or Yu for any disclosure that
remedies the deficiency in Huang and Blatchford as to the limitations in the
independent claims (Final Act. 9-13).
3 Huang discloses a corresponding structure for PMOSFET devices (]fl| 30-
36; Fig. 4).
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Application 13/799,955
features (hereafter ‘neighboring dummy features’) [120] to the next gate
level feature (e.g., another dummy feature or an active (i.e., integrated circuit
(IC) connected) gate [125] on the opposite side of an active gate
feature [110] can have a significant impact on CD [critical dimension]
control of the active gate, being particularly significant for gate CDs
beginning at the 45 nm node” (]fl[ 6, 17, 18), and “use of disclosed
neighboring dummy feature pitch and width restrictions [±15% of nominal
pitch and 0.8-1.3 x line width Wl] that design the local environment around
the neighboring dummy feature on both of its sides provide[s] an unexpected
and significant process margin improvement (e.g., CD process window
widening) for the active gate feature over conventional disregard for the
local environment around the neighboring dummy feature on the side
opposite the active gate feature” {id.). When a gate portion (240) including
two neighboring dummy features (230(a), 230(b)) is between two gate arrays
(221, 226), each comprising multiple active gate features (220 and 222-224
in gate array 221; 225 and 227-229 in gate array 226), the same narrow
pitch range (P2) separates the neighboring dummy features and the active
gate features (]fl[ 22-24; Fig. 2B). Maintaining the gate pitch “allow[s] the
scanner illumination condition to be tailored to improve process margin for
that specific narrow pitch range” (^ 23).
The Examiner finds that “[although the CD control method of
Blatchford might not be applicable to the opposite work function gates of
Huang, the multi-gate device of Blatchford would have been instructive to
one skilled in the art who was looking to improve the device density of
Huang, and would not have rendered Huang unsatisfactory for its intended
use nor change Huang’s principle [of] operation” (Ans. 3). The Examiner
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Application 13/799,955
concludes that “[i]t would have been obvious to one skilled in the art to
combine the isolation dummy gates taught by Huang with the multiple active
gates taught by Blatchford because the geometry of Blatchford allows
superior CD control while allowing the maximum density of gate lines, by
using the sub-resolution assist feature on the gate mask. Blatchford
[0006-0007]” (Final Act. 4-5).
Establishing a prima facie case of obviousness requires an apparent
reason to modify the prior art as proposed by the Examiner. See KSR Int 7
Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
The Examiner appears to be asserting that Blatchford’s disclosure that
“the new pitch effect is realized by providing a space sufficient to the nearest
gate feature for the neighboring dummy feature to allow a sub-resolution
assist feature (SRAF) to be included on the gate mask in the space provided
on the mask” (]f 7) would have provided one of ordinary skill in the art with
an apparent reason to increase the number of n-type gate electrodes (322) on
each side of Huang’s p-type dummy gate electrode (332) from one to a
plurality. The Examiner, however, does not provide evidence supporting
that assertion.
Thus, the Examiner has not established a prima facie case of
obviousness of the Appellants’ claimed MOS device.
New ground of rejection
Under 37 C.F.R. § 41.50(b) we enter the following new ground of
rejection.
Claim 17 is rejected under 35 U.S.C. § 103 as being unpatentable over
the Appellants’ admitted prior art in view of Huang.
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The Appellants’ claim 17 is in means-plus-function form. Such
means include the corresponding structure disclosed in the Appellants’
Specification and equivalents thereof. See In re Donaldson Co., 16 F.3d
1189, 1195 (Fed. Cir. 1994). The Appellants’ Specification indicates that
the first means is a first material having an n-metal or p-metal work
function, the first and second gate means are gates comprising that material,
and the second means is a second material having a work function opposite
to that of the first material (Spec. ^ 30).
The Appellants acknowledge that a CMOS device wherein a plurality
of nMOS or pMOS gates (72A/72B and 74A/74B) separated by a dummy
gate (78, 80) having the same work function as the nMOS or pMOS gates
was known in the art (Spec. ^ 30; Fig. 4). The Appellants do not
acknowledge that the prior art includes a CMOS device having a plurality of
nMOS or pMOS gates separated by a dummy gate having a work function
opposite to that of the nMOS or pMOS gates. However, Huang discloses
that separating single nMOS or pMOS gates by a dummy gate having a work
function opposite to that of the nMOS or pMOS gates ensures no leakage
current between adjacent nMOS or pMOS gates (]fl| 30, 36; Figs. 3, 4). In
view of Huang’s disclosure it would have been prima facie obvious to one of
ordinary skill in the art to replace the dummy gates in the Appellants’
acknowledged prior art CMOS device with dummy gates having a work
function opposite to that of the adjacent pluralities of nMOS or pMOS gates
to ensure no leakage current between the adjacent pluralities of nMOS or
pMOS gates.
We leave it to the Examiner to address the other claims.
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DECISION/ORDER
The rejections under 35 U.S.C. § 103 of claims 1-5, 8, 9, 11-13,
and 25 over Huang in view of Blatchford and Anderson, claims 6 and 7 over
Huang in view of Blatchford, Anderson and Holst, and claim 10 over Yu in
view of Huang, Blatchford and Anderson are reversed. Under
37 C.F.R. § 41.50(b) a new rejection of claim 17 has been entered.
It is ordered that the Examiner’s decision is reversed.
This decision contains a new ground of rejection pursuant to
37 C.F.R. §41.50(b).
37 C.F.R. § 41.50(b) provides that the Appellants, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of the
following two options with respect to the new ground of rejection to avoid
termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new evidence relating
to the claims so rejected, or both, and have the matter
reconsidered by the examiner, in which event the prosecution
will be remanded to the examiner. . . .
(2) Request rehearing. Request that the proceeding be reheard
under § 41.52 by the Board upon the same record. . . .
REVERSED: 37 C.F.R, § 41.50(b)
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