Ex Parte Yamazaki et al

Patent Trial and Appeal Board

Jun 20, 2013

10199514 (P.T.A.B. Jun. 20, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/199,514 07/22/2002 Shunpei Yamazaki 0756-7021 1526
31780 7590 06/20/2013
Robinson Intellectual Property Law Office, P.C.
3975 Fair Ridge Drive
Suite 20 North
Fairfax, VA 22033
EXAMINER
NADAV, ORI
ART UNIT PAPER NUMBER
2811
MAIL DATE DELIVERY MODE
06/20/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________
Ex parte, SHUNPEI YAMAZAKI and
YASUHIKO TAKEMURA1
____________________

Appeal 2011-003965
Application 10/199,514
Technology Center 2800
____________________
Before, SCOTT R. BOALICK, KEVIN F. TURNER, and
LYNNE E. PETTIGREW, Administrative Patent Judges.

TURNER, Administrative Patent Judge.

DECISION ON APPEAL

1 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. is the real
party in interest (App. Br. 3).
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Application No. 10/199,514

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STATEMENT OF CASE2
Appellants appeal under 35 U.S.C. § 134 from a final rejection of
claims 28-30, 32-42, 44-60, 62-160, 162, 164, 165, 167-171, 176, 177, 179-
181, and 183. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

THE INVENTION
Appellants’ disclosure relates to doping in a semiconductor memory
device (Abs.). The methodology for creating the device seeks to reduce
diffusion problems associated with the customary doping processes (Spec.
pp. 1-4).
Claim 28, reproduced below, is illustrative of the claimed subject
matter:
28. A semiconductor device comprising:
a semiconductor substrate;
a floating gate formed over said semiconductor substrate;
a control gate formed over and insulated from said
floating gate;
at least first and second impurity regions formed in said
semiconductor substrate with a channel forming region
therebetween wherein said first impurity region has a depth not
larger than 0.1 μm,
wherein a bottom face of said floating gate is located
over a level of a top surface of said first impurity region,

2 Our decision will make reference to the Appellants’ Appeal Brief (“App.
Br.,” filed August 30, 2010) and Reply Brief (“Reply Br.,” filed January 6,
2011), and the Examiner’s Answer (“Ans.,” mailed October 14, 2010).
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wherein a channel length of said semiconductor device is
0.3 μm or less and said floating gate does not overlap said first
impurity region, and
wherein said first impurity region is formed by using said
control gate as a mask.
(App. Br., Claims Appendix 54).

RELATED APPEALS
This application is related to reexamination control No. 90/007,872,
involving U.S. Patent No. 6,424,008 B1, where an appeal from final
rejection of the claims in that proceeding was taken, Appeal No. 2010-
002325, with a decision reversing the Examiner’s rejection, mailed on
October 26, 2010.

CLAIM REJECTIONS
The prior art references relied upon by the Examiner in rejecting the
claims are:
Riseman US 4,419,809 Dec. 13, 1983
Nishizawa US 4,660,062 Apr. 21, 1987
Mukherjee US 4,698,787 Oct. 6, 1987
Wu US 4,794,565 Dec. 27, 1988
Hsu US 4,841,347 Jun. 20, 1989

W.J. Spencer & T.E. Seidel, “National Technology Roadmaps: the U.S.
Semiconductor Experience,” 4th Int’l Conference on Solid-State and
Integrated Circuit Tech. 211-220 (October 24-28, 1995) (“Spencer”).

Paul S. Peercy, “The Drive to Miniaturization,” 406 Nature 1023-1026
(August 31, 2000) (“Peercy”).

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Application No. 10/199,514

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Lidia Lukasiak et al., “Silicon microelectronics: where we have come
from and where we are heading,” J. Telecomm. & Info. Tech. 7-14 (January
2004) (“Lukasiak”).

The Examiner makes the following rejections:
Claims 28-30, 32-42, 44-60, 62-160, 162, 164, 165, 167-171, 176,
177, 179-181, and 183 rejected under 35 U.S.C. § 101 as being inoperative
and therefore lacking in utility (Ans. 4-5);
Claims 28-30, 32-42, 44-60, 62-160, 162, 164, 165, 167-171, 176,
177, 179-181, and 183 rejected under 35 U.S.C. § 112, second paragraph, as
being indefinite (Ans. 5); and
Claims 28-30, 32-42, 44-60, 62-160, 162, 164, 165, 167-171, 176,
177, 179-181, and 183 rejected under 35 U.S.C. § 103(a) as unpatentable
over Mukherjee, Riseman, Wu, Nishizawa and Hsu, considered with Peercy,
Lukasiak, and Spencer (Ans. 5-13).

ISSUES3
We take claim 28 as representative of all of the pending claims. See
37 C.F.R. § 41.67(c)(1)(vii).
1. Is the structure recited in claim 28 inoperative and thus lacking in
utility under 35 U.S.C. § 101?
2. Is claim 28 indefinite under 35 U.S.C. § 112, second paragraph?

3 We have considered in this decision only those arguments that Appellants
actually raised in the Briefs. Arguments which Appellants could have made
but chose not to make in the Briefs are deemed to be waived. See 37 C.F.R.
§ 41.37(c)(1)(vii).
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3. Does the combination of Mukherjee, Riseman, Wu, Nishizawa and
Hsu, considered with Peercy, Lukasiak, and Spencer, teach or suggest the
subject matter of claim 28 under 35 U.S.C. § 103(a)?

FINDINGS OF FACT
1. The Specification of the instant application is directed to
semiconductor memory devices having floating gates, where the
methodology for creating the devices seeks to reduce diffusion
problems associated with the customary doping processes (Spec.
pp. 1-4; Abs.).
2. The Specification of the instant application provides that the
“present invention enables stable fabrication of MOS devices
having a channel length of 1.0 µm or less, typically from 0.1 to 0.3
µm, and a shallow impurity region 0.1 µm or less in depth.” (Spec.
p. 20).
3. Claim 28 recites, in part, a semiconductor memory device having a
first impurity region with a depth not larger “than 0.1 µm,” and
that the “channel length of said semiconductor device is 0.3 µm or
less” (Br. Claim App’x 54).
4. Mukherjee is directed to an electrically erasable programmable
memory device which is programmable in the manner of an
EPROM and erasable in the manner of an EEPROM (Abs.).
5. Riseman is directed to a method of producing a sub-micron gate
length field effect transistor device (Abs.), where the channel
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length can be 0.3 microns or less (col. 6, ll. 18-44) and having an
impurity region less than 0.1 microns in depth (col. 7, l. 45).
6. Wu is directed to an electrically programmable memory device
employing source side injection, where the channel length is 1
micron or less (col. 6, ll. 12-13).
7. Nishizawa is directed to an insulated gate transistor having reduced
channel length (Abs.). In one embodiment, the source and drain
regions are formed as very shallow regions with 100 Å to 1,000 Å
in depth (col. 9, ll. 3-5). Channel lengths as short as 400 to 500 Å
can be produced (col. 8, ll. 61-64).
8. Hsu is directed to a MOSFET with very shallow source and drain
regions (Abs.). The depths are disclosed to less than 100 nm (col.
1, ll. 44-49).

PRINCIPLES OF LAW
“Section 103 forbids issuance of a patent when ‘the differences
between the subject matter sought to be patented and the prior art are such
that the subject matter as a whole would have been obvious at the time the
invention was made to a person having ordinary skill in the art to which said
subject matter pertains.’” KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 406
(2007).
“[A] court must ask whether the improvement is more than the
predictable use of prior art elements according to their established
functions.” Id. at 417.
When there is a design need or market pressure to solve a
problem and there are a finite number of identified, predictable
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solutions, a person of ordinary skill has good reason to pursue
the known options within his or her technical grasp. If this leads
to the anticipated success, it is likely the product not of
innovation but of ordinary skill and common sense.
Id. at 420.

ANALYSIS
Rejection under 35 U.S.C. § 101
The Examiner finds that all of the claims, including claim 28, recite
that the limitation of “a channel length of said semiconductor device is 0.3
μm or less” reads on a channel length of zero or close to zero, such that the
device claimed is inoperative if the channel length is zero (Ans. 4-5).
Appellants argue that the Examiner is interpreting the claims in a manner
inconsistent with the Specification (Reply Br. 11). We agree with
Appellants.
While the Examiner emphasizes that the Specification provides no
evidence of an operative embodiment therein “which can operate in the
entire claimed range of ‘0.3 microns or less’” (Ans. 16-17), that is not a
requirement for utility. There is no requirement that a full range recited in a
claim must be supported by working embodiments. As the predecessor of
our reviewing court stated:
[C]laims are not to be considered in a vacuum, “but always in
light of the teachings of the prior art and of the particular
application disclosure as it would be interpreted by one
possessing the ordinary level of skill in the pertinent art.”
When considered in the light of the prior art and the
specification, claims otherwise indefinite may be found
reasonably definite.
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In re Kroekel, 504 F.2d 1143, 1146 (CCPA 1974)(citing In re Moore, 439
F.2d 1232 (CCPA 1971)).
A rejection based on indefiniteness, or utility, is not necessarily valid
simply because the “claims may be read in theory to include compositions
that are impossible in fact to formulate.” Id. The fact that claim 28 could be
made to read upon a device with a zero or close to zero channel length, i.e.,
an inoperative device, does not require that the claim be found to have no
utility. Read in the context of the Specification (FF 3), a practical range less
than 0.3 microns can be determined, such that one of ordinary skill in the art
would not have viewed the claim as reading upon non-working
embodiments. As such, we conclude that claim 28 is not inoperative and
thus does not lack utility under 35 U.S.C. § 101.

Rejection under 35 U.S.C. § 112, second paragraph
The Examiner finds that claim 28 is indefinite because it is unclear
whether or if the claim limitation “channel length” is related to the recited
“channel forming region,” or that the claim is indefinite because the channel
length is not recited to have a “lower limit” (Ans. 5, 16-18). Appellants
argue that one of ordinary skill in the art would have understood that a
channel is formed in a channel forming region of the device (Reply Br. 12).
We agree with Appellants.
While it may be clearer to have claim 28 recite, for example, “a
channel length of a channel, formed by said channel forming region, is 0.3
μm or less,” or some other formulation, we conclude that ordinarily skilled
artisans would have understood that the channel is formed in the channel
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forming region, and that the channel length is the length of that channel.
While the Examiner argues that the claims, and thus claim 28, do not require
that the “channel length” refer to the specific transistor recited in claims, i.e.,
it could be the length of a channel in some other transistor in the same
semiconductor device (Ans. 19-20), we conclude that this goes to the
breadth of the claim, not to the definiteness of the claim. The fact that the
Examiner can read the channel length onto some other transistor in the
device means that that claim is broad enough to read upon such devices, and
is an invitation to the Examiner to find prior art that would fit under such a
broad interpretation. It does not mean that the claims, and hence claim 28, is
indefinite because of such breadth.
With respect to the “lower limit” of the channel length, we have
addressed the same argument in the above section and need not repeat it
here. As such, we conclude that claim 28 is not indefinite under 35 U.S.C.
§ 112, second paragraph.

Rejection under 35 U.S.C. § 103(a)
Appellants argue that the “Official Action has not set forth sufficient
reasons why one of skill in the art at the time of the present invention would
have had a reason to combine the prior art of record to achieve the features
of the present invention” (App. Br. 36). Appellants argue that the
miniaturization of semiconductor devices requires more than making the
components of the device smaller (App. Br. 39-40). The Examiner finds that
“[i]t is well known in the art to reduce the depths of the source and drain
regions and the widths of the channel regions, subjected to routine
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experimentation and optimization. Therefore, the result of reducing these
parameters is expected.” (Ans. 29). We agree with Appellant.
The Examiner relies upon Peercy, Lukasiak, and Spencer to show that
market forces and design need in the semiconductor industry was toward
miniaturization. Even accepting that proposition, a semiconductor device is
not miniaturized through rote reduction, as would be performed on a copy
machine. As Appellants have argued, “a simple generalized assertion that
the device could be scaled in size falls far short of providing sufficient
motivation and a reasonable expectation of success to one of ordinary skill
in the art contemplating such changes” (App. Br. 39). In other words,
finding that devices likely will continue to miniaturize, does not provide
motivation of how to do that specifically. Additionally, to simply say that
things are going to get smaller and to look at trend lines after the fact does
not establish how the process actually occurs.
As Appellants have pointed out (App. Br. 38-39), the device in
Mukherjee has layers with specific areas and thicknesses, and unforeseen
affects can occur through mere reduction in the sizes of all of those layers.
The semiconductor art is replete with patents directed to methods and
devices that allow for more devices to be placed on a semiconductor surface
and resolve the consequences of further integration. While we have no
doubt that the device in Mukherjee could be reduced in size, perhaps even in
view of Riseman, Wu, Nishizawa and Hsu, we find no provision for why
such a reduction would occur, other than the market forces and design need
in the semiconductor industry provided by the Examiner.
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As Appellants have argued: “Moore’s Law does not tell one of
ordinary skill in the art at the time of the present invention how to
miniaturize a device” (App. Br. 40). The Examiner does not find this
argument to be persuasive (Ans. 29), but we find the analogy to be apt and
helpful. Like Moore’s Law, the trends and market forces relied upon by the
Examiner predict results without providing a basis for reaching those results.
Purveyors and consumers of science fiction literature and cinema no doubt
could have some idea of what our world would look like in a hundred years,
but that would provide no roadmap for reaching such a possible future. The
Examiner's reliance on such general trends to show specific changes is not
sufficient here to show obviousness under 35 U.S.C. § 103.
The Examiner also finds that making a device smaller is obvious and
cites several cases to buttress that point (Ans. 28). However, the citations
are directed to improvements which are “technology-independent,” as
argued by Appellants (Reply Br. 9-10). In fact, the court in Leapfrog
(Leapfrog Enterprises, Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1161 (Fed.
Cir. 2007) stated that “Leapfrog presents no evidence that the [improvement]
was uniquely challenging or difficult for one of ordinary skill in the art.” Id.
at 1162. In the instant case, Appellants have provided many obstacles that
would need to be overcome to accomplish the miniaturization, (App. Br. 20-
24), which the Examiner has not countered. The suggestion that electronic
devices will continue to miniaturize does not provide an explanation of how
the process is accomplished. As such, we conclude that trends in
miniaturization do not compel the modifications envisioned by the Examiner
in the prior art rejection of the claims.
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Given that we do not find the trends (Peercy, Lukasiak, and Spencer)
relied upon by the Examiner to be sufficient , we do not find the Examiner’s
assertion that source/drain regions of Mukherjee (FF 4) can be reduced to
“not larger than 0.1 µm,” in view of Riseman, Wu, Nishizawa and Hsu (FF
5-8) to be supported.
We also do not find it dispositive that Riseman and Nishizawa teach
that diffusion regions can have the depths disclosed in those references (FF
5, 7). The existence of diffusion regions having such depths does not
establish obviousness without some reason to incorporate such depths into
Mukherjee. “[I]nventions in most, if not all, instances rely upon building
blocks long since uncovered, and claimed discoveries almost of necessity
will be combinations of what, in some sense, is already known.” KSR, 550
U.S. at 418-419.
We note that we need not address whether Peercy, Lukasiak, and
Spencer are prior art to the instant claim, since their application to show a
bare trend does not provide a motivation required by the rejections.

CONCLUSIONS
1. The structure recited in claim 28 is not per se inoperative and thus
it does not lack utility under 35 U.S.C. § 101;
2. Claim 28 is not indefinite under 35 U.S.C. § 112, second paragraph;
and
3. The combination of Mukherjee, Riseman, Wu, Nishizawa and Hsu,
considered with Peercy, Lukasiak, and Spencer, does not render claim 28
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obvious under 35 U.S.C. § 103(a) under the analysis of the Examiner in the
final rejection.
DECISION
We reverse the Examiner’s rejection of claims 28-30, 32-42, 44-60,
62-160, 162, 164, 165, 167-171, 176, 177, 179-181, and 183.

REVERSED
Vsh