Ex Parte YAMAMURA

Patent Trial and Appeal Board

Aug 14, 2018

13923742 (P.T.A.B. Aug. 14, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/923,742 06/21/2013
97149 7590 08/16/2018
Maschoff Brennan
1389 Center Drive, Suite 300
Park City, UT 84098
FIRST NAMED INVENTOR
Kuni Y AMAMURA
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
S 1202.10378US01 5319
EXAMINER
LAM, TUAN THIEU
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
08/16/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docket@mabr.com
info@mabr.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KUNI Y AMAMURA
Appeal 2018-001321
Application 13/923,742
Technology Center 2800
Before ADRIENE LEPIANE HANLON, N. WHITNEY WILSON, and
MERRELL C. CASHION, JR., Administrative Patent Judges.
WILSON, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner's September 13, 2016, decision rejecting claims 1-3 and 5-15 as
unpatentable under 35 U.S.C. § 103(a). We have jurisdiction over the
appeal under 35 U.S.C. § 6(b).
We affirm.
1 The real party in interest is identified as Seiko Epson Corporation (Br. 4 ).
Appeal 2018-001321
Application 13/923,742
CLAIMED SUBJECT MATTER
Appellant's invention is directed a shift register which includes first
type D latches in the odd-numbered stage and second type D latches in the
even-numbered stage (Abstract). A pass gate of the first type D latch and a
memory controller of the second type D latch are made from a first
conductivity type transistor, and a memory controller of the first type D latch
and a pass gate of the second type D latch are made from a second
conductivity type transistor (id.). Details of the claimed invention are set
forth in representative claim 1, which is reproduced below from the Claims
Appendix of the Brief (emphasis added):
1. A shift register circuit comprising:
first top-th[] (pis an integer that is 2 or greater) D
latches; and
a clock line,
wherein each of the first to p-th D latches includes,
a input portion, and
a output portion,
wherein the output portion of the i-th (i is an integer from
1 to (p - 1)) D latch and the input portion of the (i + 1)-th D
latch are electrically connected to each other,
wherein each of the first to p-th D latches includes, at
least
a pass gate,
first to 2k-th (k is an integer that is 1 or greater) inverters,
and
a memory controller,
wherein the pass gate and the first to 2k-th inverters are
electrically connected in series between the input portion and
the output portion, the memory controller is electrically
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Application 13/923,742
connected in parallel to the first to 2k-th inverters between the
pass gate and the output portion, and a control electrode of the
pass gate and a control electrode of the memory controller are
electrically connected to the clock line,
wherein the first top-th D latches in the odd-numbered
stage are first type D latches and the first to p-th D latches in
the even-numbered stage are second type D latches,
wherein the pass gate of the first type D latch is made
from a first conductivity type transistor and the memory
controller of the first type D latch is made from a second
conductivity type transistor, the first conductivity type
transistor is an N-type transistor and the second conductivity
type is a P-type transistor,
wherein the pass gate of the second type D latch is made
from the second conductivity type transistor, and the memory
controller of the second type D latch is made from the first
conductivity type transistor,
wherein the first to p-th D latches are driven by a single
phase clock signal supplied through the clock line,
when the single phase clock signal is active, the pass gate
of the first type of D latch allows the inputting of new data and
the storage circuit of the first type of D latch functions as a
buff er circuit while the pass gate of the second type of D latch
disallows the inputting of new data and the storage circuit of the
second type of D latch functions as a storage circuit, whereas
when the single phase clock signal is inactive, the pass gate of
the second type of D latch allows the inputting of new data and
the storage circuit of the second type of D latch functions as a
buffer circuit while the pass gate of the first type of D latch
disallows the inputting of new data and the storage circuit of the
first type of D latch functions as a storage circuit, and
wherein a period in which the first type D latch is made
active is shorter than a period in which the second type D latch
is made active.
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Application 13/923,742
REJECTIONS
1. Claims 1-3, 5-11, and 15 are rejected under 35 U.S.C. § I03(a)
as unpatentable over Bancel2 in view of Tso, 3 Aoki, 4 and Shimozono. 5
2. Claim 12 is rejected under 35 U.S.C. § I03(a) as unpatentable
over Bancel, in view of Tso, Shimozono, Uemura, 6 and Yoshizawa. 7
3. Claim 13 is rejected under 35 U.S.C. § I03(a) as unpatentable
over Bancel, in view of Tso, Shimozono, and Uemura.
4. Claim 14 is rejected under 35 U.S.C. § I03(a) as unpatentable
over Bancel, in view of Tso, Shimozono, and Uemura.
DISCUSSION
Appellant's arguments are solely directed to the rejection of claim 1
(see, Br. 9-12). Accordingly, our analysis will focus on the rejection of
claim 1 over Bancel in view of Tso, Aoki, and Shimozono. The remaining
claims will stand or fall with claim 1. 37 C.F.R. § 4I.37(c)(l)(iv) (2013).
Appellant's arguments focus on the Examiner's findings and
conclusions with regard to the obviousness of the last limitation of claim 1:
"wherein a period in which the first type D latch is made active is shorter
than a period in which the second type D latch is made active." The
Examiner finds that Aoki teaches that n-type transistors (which correspond
2 Bancel et al., US 8,466,727 B2, issued June 18, 2013.
3 Tso et al., US 2008/0253500 Al, published October 16, 2008.
4 Aoki, US 5,013,937, issued May 7, 1991.
5 Shimozono et al., US 5,497,114, issued March 5, 1996.
6 Uemura, US 6,242,957 Bl, issued June 5, 2001.
7 Yoshizawa, US 7,489,174 B2, issued February 10, 2009.
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Application 13/923,742
to the claimed first type D-latch) are faster than p-type transistors (which
correspond to the claimed second type D-latch) (Non-Final Act. 5). The
Examiner determines that one of skill in the art would, accordingly, have
recognized that a p-type transistor in a master-slave configuration would
have to be turned on for a longer duration to compensate for the slower
response of the p-type transistor in order to maintain a synchronous
operation between the master and slave stages (id.). The Examiner
concludes that it would, therefore, have been obvious to have an uneven
duty cycle clock signal so that then-type transistor within the first-type D-
latch is turned on with a shorter duration than the p-type transistor in the
second-type D-latch in order to maintain a synchronous operation (id.).
Appellant makes two arguments that the foregoing determination is
reversibly erroneous: (1) even if Aoki teaches that n-type transistors are
faster than p-type transistors, Aoki does not teach or suggest lengthening or
shortening the period for which the transistors are made active in order to
compensate for their relative speeds (Br. 11 ); (2) altering the periods for
which the transistors are active would alter the manner in which the circuit
operates (id. at 11-12).
We have carefully considered the foregoing arguments, but do not
find them persuasive of reversible error.
With regards to argument ( 1 ), there is no dispute that Aoki teaches
that that n-type transistors are faster (i.e. have a faster switching speed) than
p-type transistors (see, e.g. Aoki 1:16-18). Although the Examiner does not
find that Aoki discloses the claim limitation at issue, the Examiner finds that
"[i]t was also known in the art that it is important that master-slave latches
connected in series are operated synchronously in order to provide output
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Application 13/923,742
signals at a desired timing" and that "[ s ]ynchronous operation of the master-
slave latches requires the input clock signal to have the required duty cycle"
(Ans. 19). Appellant does not challenge these findings. The Examiner's
determination that a person of skill in the art would have been motivated to
have the p-type transistors in a master-slave configuration turned on for a
longer duration than the n-type transistors to compensate for the slower
response times of the p-type transistors to maintain synchronous operation
between the master and slave stages (Ans. 19) is supported by a
preponderance of the evidence of record. That is, the Examiner has
adequately demonstrated why the art would have suggested making the first
type D latch active for a shorter period of time than the second type D latch.
With regards to argument (2), Appellant contends that varying the
period in which the two latches are made active makes the circuit operate
differently than if the latches were active for the same amount of time (Br.
11-12). Appellant does not make clear why this is a reversible error.
Moreover, as found by the Examiner, the claimed circuit would still operate
even if the active periods for the two types of latches were the same (Ans.
20).
In any event, the Examiner has adequately established why a person
of skill in the art would have modified the cited art in order to have the first
type D latch be active for a shorter period than the second type D latch.
The Examiner's rejection of claim 1 is affirmed, as are the remaining
rejections.
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CONCLUSION
We AFFIRM the rejection of claims 1-3, 5-11, and 15 under
35 U.S.C. § 103(a) as unpatentable over Bancel in view of Tso, Aoki, and
Shimozono.
We AFFIRM the rejection of claim 12 under 35 U.S.C. § 103(a) as
unpatentable over Bancel, in view of Tso, Shimozono, Uemura, and
Yoshizawa.
We AFFIRM the rejection of claim 13 under 35 U.S.C. § 103(a) as
unpatentable over Bancel, in view of Tso, Shimozono, and Uemura.
We AFFIRM the rejection of claim 14 under 35 U.S.C. § 103(a) as
unpatentable over Bancel, in view of Tso, Shimozono, and Uemura.
No time period for taking any subsequent action in connection with
this appeal maybe extended under 37 C.F.R. § 1.136(a)(l).
AFFIRMED
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