Ex Parte Yamamoto et al

Patent Trial and Appeal Board

Feb 25, 2014

11461855 (P.T.A.B. Feb. 25, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte YUKI YAMAMOTO, JUN HARADA,
HIROSHI TAKAGI, and KATSURO HIRAYAMA
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Appeal 2011-010660
Application 11/461,855
Technology Center 2800
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Before CATHERINE Q. TIMM, ROMULO H. DELMENDO, and
MICHAEL P. COLAIANNI, Administrative Patent Judges.

TIMM, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF CASE
Appellants request review of the Examiner’s decision to reject claims
1-11 under 35 U.S.C. § 112, ¶¶ 1 and 2. We have jurisdiction under
35 U.S.C. §§ 6(b) and 134.
We REVERSE.
The claims are directed to an electronic component comprising,
among other things, a core substrate, at least one active chip element, and at
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Application 11/461,855

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least one passive chip element (see, e.g., claim 1). As shown in Figure 2a,
the active chip elements 12 are mounted on one side (upper or first main
surface) of the core substrate 11, while the passive chip elements 13 are
mounted on the other side (lower or second main surface) of the core
substrate 11 (Spec. ¶ 0033). The elements 12 and 13 are said to be
“mounted at predetermined locations in the circuit patterns” (id.). All of the
claims require that “no passive chip element is disposed on the first main
surface and no active chip element is disposed on the second main surface”
of the core substrate (see, e.g., claim 1).
The Examiner’s rejections are based on an interpretation of “passive
chip element” as encompassing the circuit patterns (Ans. 4).
With regard to the enablement rejection under 35 U.S.C. § 112, ¶ 1,
the Examiner concludes that the claims do not enable one of ordinary skill in
the art to make and use the device because the language “no passive chip
element” excludes the presence of circuit patterns and Appellants do not
disclose how the device can operate without circuit patterns on the first main
surface of the core substrate (id.).
With regard to the indefiniteness rejection under 35 U.S.C. §112, ¶ 2,
the Examiner determines that the claims are unclear as to whether passive
elements are formed on the first main surface “because circuit pattern [sic] is
not active elements, and thus being render [sic] a passive element.” (Id.)
We agree with Appellants that the Examiner has misinterpreted
“passive chip element” as including the circuit patterns that connect
electronic components (Br. 13 and Reply Br. 5-6). Throughout the
Specification, the passive chip elements are differentiated from circuit
patterns. For instance, paragraph 19 of the original Specification describes
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active chip elements 12 (shown in Fig. 1) as, for example, semiconductor
elements, passive chip elements 13 as, for example, capacitors, inductors,
and resistors. Both the active elements, which reside on the upper surface of
the core substrate 11, and the passive elements, which reside on the lower
surface of the core substrate 11, are disposed at locations in a circuit pattern
(id.). Paragraph 33 states that the active chip elements and passive chip
elements “are mounted” at locations in the circuit patterns.
During examination, “‘claims . . . are to be given their broadest
reasonable interpretation consistent with the specification, and . . . claim
language should be read in light of the specification as it would be
interpreted by one of ordinary skill in the art.’” In re Am. Acad. of Sci. Tech.
Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004).
While we agree with the Examiner that the Specification is written
such that “capacitors, inductors, and resistors” are merely examples of
passive chip elements (Ans. 7), we also agree with Appellants that it is
unreasonable to interpret “passive chip element” to include connection
structures such as circuit pattern lines and vias when reading the claim
language in light of the Specification as an ordinary artisan would interpret
the language (Br. 13). The lines and vias are merely the electron highways
between the various active semiconductor elements and the passive chip
elements. Passive chip elements are elements such as capacitors, inductors,
and resistors, and must have a structure different than that of lines and vias.

CONCLUSION
We do not sustain the Examiner’s rejections.
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DECISION
The Examiner’s decision is reversed.

REVERSED

cdc