Ex Parte Yadav

Board of Patent Appeals and Interferences

Nov 13, 2009

10891339 (B.P.A.I. Nov. 13, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte RISHI YADAV

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Appeal 2009-004236
Application 10/891,3391
Technology Center 2100
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Decided: November 13, 2009
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Before ST. JOHN COURTENAY III, CAROLYN D. THOMAS, and
STEPHEN C. SIU, Administrative Patent Judges.

THOMAS, Administrative Patent Judge.

DECISION ON APPEAL

1 Application filed July 14, 2004. The real party in interest is Cypress
Semiconductor Corporation.
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Application 10/891,339

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I. STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from a final rejection
of claims 1-202 mailed July 20, 2007, which are all the claims pending in the
application. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.

A. INVENTION
Appellant invented a system and method for a First-In First-out
(FIFO) memory error circuit having a read pointer coupled to a FIFO
memory. The read pointer has a logic high output once every FIFO memory
cycle. A write pointer is coupled to the FIFO memory and has a logic high
output once every FIFO memory cycle. An error detector has a first input
coupled to the read pointer and a second input coupled to the write pointer.
(Spec. 16, Abstract.)

B. ILLUSTRATIVE CLAIMS
The appeal contains claims 1-20. Claims 1, 8, and 15 are independent
claims. Claims 1, 8, and 15 are illustrative:
1. A FIFO memory error circuit, comprising:
a read pointer control logic coupled to a FIFO
memory having a read output that is true once every read cycle
of the FIFO memory;

2 A Notice of Panel Decision from a Pre-Appeal Brief Review dated
October 10, 2007 altered the status of claims 2-5, 10, 11, 14, 18, and 20 from
rejected to objected to.
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a write pointer control logic coupled to a FIFO
memory having a write output that is true once every write
cycle of the FIFO memory; and
en error detection circuit having a first input
coupled to the read output and a second input coupled to the
write output.

8. A method of determining a FIFO memory error,
comprising the steps of:
a) determining a read pointer count in a FIFO
memory;
b) determining a write pointer count in the FIFO
memory; and
c) determining if the read pointer count is within a
clock cycle of the write pointer count.

15. A FIFO memory error circuit, comprising:
a read pointer coupled to a FIFO memory having a
logic high output once every FIFO memory cycle;
a write pointer coupled to the FIFO memory
having a logic high output once every FIFO memory cycle; and
an error detector having a first input coupled to the
read pointer and a second input coupled to the write pointer.

C. REFERENCES
The references relied upon by the Examiner as evidence in rejecting
the claims on appeal are as follows:
Cheng US 2004/0098654 A1 May 20, 2004
Miyamoto US 6,810,468 B2 Oct. 26, 2004

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D. REJECTIONS
The Examiner entered the following rejections which are before us for
review:
(1) Claim 1 is rejected under 35 U.S.C. § 102(e) as being anticipated
by Cheng; and
(2) Claims 6-9, 12, 13, 15-17, and 19 are rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Cheng in view of Miyamoto.

II. FINDINGS OF FACT
The following findings of fact (FF) are supported by a preponderance
of the evidence.
Cheng
1. Cheng discloses that “the FIFO memory circuit further includes a
memory unit, a write control unit, a read control unit and a flag logic unit. . .
. The write control unit couples with the memory unit and has a write
pointer. . . . The read control unit couples with the memory unit and has a
read pointer . . . .” (¶ [0007].)
2. Cheng discloses that the read/write pointers have a value that can
trigger a memory full/empty flag. (¶ [0007].)

Miyamoto
3. Miyamoto discloses that “[t]he write pointer 21, read pointer 22
and previous read pointer 28 count up by 1 on the falling edges of the write
signal WR or the read signal RD.” (Col. 9, ll. 46-48.)
4. Miyamoto discloses that “the value of the read pointer 22 always
indicates the next read address.” (Col. 5, ll. 43-44.)
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III. PRINCIPLES OF LAW
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005), citing Minn. Mining & Mfg.
Co. v. Johnson & Johnson Orthopaedics, Inc., 976 F.2d 1559, 1565 (Fed.
Cir. 1992).
Anticipation of a patent claim requires a finding that the claim
at issue ‘reads on’ a prior art reference. In other words, if
granting patent protection on the disputed claim would allow
the patentee to exclude the public from practicing the prior art,
then that claim is anticipated, regardless of whether it also
covers subject matter not in the prior art.
Atlas Powder Co. v. IRECO, Inc., 190 F.3d 1342, 1346 (Fed Cir. 1999)
(internal citations omitted).
“What matters is the objective reach of the claim. If the claim
extends to what is obvious, it is invalid under § 103.” KSR Int’l Co. v.
Teleflex, Inc., 550 U.S. 398, 419 (2007). To be nonobvious, an
improvement must be “more than the predictable use of prior art elements
according to their established functions.” Id. at 417.

IV. ANALYSIS
Grouping of Claims
In the Brief:
Group I: Appellant argues claim 1 separately (App. Br. 8).
Group II: Appellant essentially argues claims 6, 7, 12, 13, 15-17,
and 19 as a group (App. Br. 9-13). For claims 6, 7, 12, 13, 16, 17, and 19,
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Appellant repeats the same argument made for claim 15. We will, therefore,
treat claims 6, 7, 12, 13, 16, 17, and 19 as standing or falling with claim 15.
Group III: Appellant essentially argues claims 8 and 9 as a group
(App. Br. 9-10.).
See 37 C.F.R. § 41.37(c)(1)(vii). See also In re Young, 927 F.2d 588,
590 (Fed. Cir. 1991).

The Anticipation Rejection
We first consider the Examiner’s rejection of claim 1 under 35 U.S.C.
§ 102(e) as being anticipated by Cheng.

Group I
Claim 1
Appellant contends that the read pointer (rptr Fig. 2) and write pointer
(wptr Fig. 2) of Cheng are not even coupled to the error correction code
(ECC) circuit 230. (App. Br. 8.) In addition, the read/write pointer of
Cheng is a number not a logic true. (Id.) Appellant further contends that
“[a]n ECC circuit uses an error code to determine errors, not the read and
write pointer and that is why the read and write pointer of Chen[g] are not
coupled to the ECC circuit 230 . . . .” (Id.)
We find that Appellant’s above-noted arguments are not
commensurate with the actual scope of instant claim 1. For example,
Claim 1 does not require that the read and write pointers be coupled to an
ECC circuit. Instead, Claim 1 merely recites, inter alia, “a read pointer
control logic coupled to a FIFO memory” and “a write pointer control logic
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coupled to a FIFO memory.” Here, we find that Cheng discloses a read
pointer and a write pointer that are coupled to the FIFO memory (FF 1).
In addition, contrary to Appellant’s arguments, Claim 1 does not
require that the read/write pointer be a “logic” true. Instead, Claim 1 merely
recites “a read output that is true” and “a write output that is true.” The term
“true” signifies any output that is fully realized, regardless of if it’s a logic
true, a high, or a low. Similarly, Cheng discloses that the read/write pointers
have a “value” that can be used to set memory full/empty flags (FF 2). Such
values can be seen as “true” values.
Finally, contrary to Appellant’s arguments, Claim 1 does not require
that the error detector circuit use the read/write outputs to determine errors.
Instead, Claim 1 merely recites “an error detection circuit having a first input
coupled to the read output and a second input coupled to the write output.”
However, Claim 1 does not describe how these inputs are being used or if
they are being used to determine errors. Only a “structural connection” is
being claimed. Cheng discloses in Figure 2 such a structural connection
between read/write outputs (rptr/wptr) and the inputs to an error detection
circuit 224.
While we agree with Appellant’s statement concerning the “present
application,” it is the claimed invention that the Examiner has evaluated and
rejected and which we review. Here, Appellant’s argument does not show
error in the Examiner's evaluation of the claimed invention and the
application of the teachings of Cheng thereto.
Thus, Appellant has not persuaded us of error in the Examiner’s
conclusion of anticipation for representative claim 1. Therefore, we affirm
the Examiner’s § 102 rejection of independent claim 1.
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The Obviousness Rejection
We now consider the Examiner’s rejection of the claims under
35 U.S.C. § 103(a).

Group II
Claim 6, 7, 12, 13, 15-17, 19
Appellant contends that “the read pointer of Cheng is a number not a
logic true. Chen[g] never discusses that the read pointer is true at the start of
the read cycle. Miyamoto does not show a read pointer with a logic high
either.” (App. Br. 9.) Appellant further contends that “[s]ince Cheng does
not have a write pointer with a logic high, he does not have one that is
initiate[d] true near the middle of the cycle. Miyamoto does not show a
write pointer with a logic high either.” (Id.)
The Examiner found that while Cheng does not explicitly address a
logic HIGH output, Miyamoto explicitly teaches read/write rising/falling
(i.e., HIGH and LOW logics) via clocking signals in supporting the error
detection (Ans. 11-12).

Issue: Has Appellant shown that the Examiner erred in finding that
the combination of Cheng and Miyamoto discloses a read/write pointer
having a logic high output once every FIFO memory cycle?

Here, Appellant contends that the combined teachings of Cheng and
Miyamoto fail to disclose a logic/true/high at the claimed instances in the
read/write cycles. For example, Claim 15 requires “a logic high output once
every FIFO memory cycle”; Claim 6 requires “initiated true near a start of
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the read cycle”; Claim 7 requires “initiated true near a middle of the write
cycle” etc. In response, the Examiner predominantly relies upon Miyamoto
to teach this clocking relationship with the true/high outputs.
For example, Miyamoto discloses that the write/read pointers count up
by 1 on the falling edges of the write signal WR or the read signal RD (FF
3). In other words, if we are to interpret a write signal as signifying a write
cycle (which is reasonable), Miyamoto teaches that write pointers count up
during a write cycle. However, Miyamoto discloses that the value of the
pointer always indicates a read address (FF 4). An address is
distinguishable from a “logic high.” In this regard, the Examiner has not
identified any timing features in either Cheng or Miyamoto that shows a
logic high output from the read/write pointers once every FIFO memory
cycle.
Similarly, the Examiner has not shown how the cited references teach
initiating a “true” near a start of the read cycle or near a middle of the write
cycle. Instead, the Examiner has merely directed our attention to falling
edges of read/write signals and how that relates to the read/write pointers
address count up. However, there is no clear indication in the Examiner’s
findings how such “addresses” are indicative of a “true” or “logic high”
during the specified times in the FIFO memory cycle, read cycle, or write
cycle.
Thus, Appellant has persuaded us of error in the Examiner’s
conclusion of obviousness for representative claim 15. Therefore, we
reverse the Examiner’s § 103 rejection of independent claim 15 and of
claims 6, 7, 12, 13, 16, 17, and 19, which stand therewith.

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Group III
Claims 8 and 9
Appellant contends that “Cheng only determines if the memory is
empty or full, element 224 of F[ig]. 2. This does not tell if the read pointer
count is within a clock cycle of the write pointer count.” (App. Br. 9-10.)
As noted supra, the Examiner has merely directed our attention to
falling edges of read/write signals and how that relates to read/write pointer
address counts. However, there is no clear indication in the Examiner’s
findings about specific timing restraints of the FIFO memory cycle, read
cycle, or write cycle and how the pointers’ address count is related thereto.
In fact, we do not find, and the Examiner has not shown, any teaching or
suggestion in the cited references that sets forth clock cycle requirements
relating to pointer counts, particularly determining if the read pointer count
is within a clock cycle of the write pointer count, as set forth in claim 8.
Thus, Appellant has persuaded us of error in the Examiner’s
conclusion of obviousness for representative claim 8. Therefore, we reverse
the Examiner’s § 103 rejection of independent claim 8 and of claim 9, which
stands therewith.

V. CONCLUSIONS
We conclude:
(1) Appellant has not shown that the Examiner erred in rejecting
claim 1; however,
(2) Appellant has shown that the Examiner erred in rejecting claims
6-9, 12, 13, 15-17, and 19.

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VI. DECISION
In view of the foregoing discussion:
(1) We affirm the Examiner’s rejection of claim 1; and
(2) We reverse the Examiner’s rejection of claims 6-9, 12, 13, 15-17,
and 19.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv) (2009).

AFFIRMED-IN-PART

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