Ex Parte Xue et al

Board of Patent Appeals and Interferences

Aug 31, 2011

11461428 (B.P.A.I. Aug. 31, 2011)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/461,428 07/31/2006 Lei Xue 0180386 3599
25700 7590 08/31/2011
FARJAMI & FARJAMI LLP
26522 LA ALAMEDA AVENUE, SUITE 360
MISSION VIEJO, CA 92691
EXAMINER
GUMEDZOE, PENIEL M
ART UNIT PAPER NUMBER
2891
MAIL DATE DELIVERY MODE
08/31/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte LEI XUE, RINJI SUGINO, YOUSEOK SUH,
HIDEHIKO SHIRAIWA, MENG DING, SHENQING FANG,
and JOONG JEON
____________________

Appeal 2009-014911
Application 11/461,428
Technology Center 2800
____________________

Before MICHAEL P. TIERNEY, STEPHEN C. SIU, and
JEFFREY B. ROBERTSON, Administrative Patent Judges.

ROBERTSON, Administrative Patent Judge.

DECISION ON APPEAL

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Application 11/461,428

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STATEMENT OF CASE
Appellants appeal under 35 U.S.C. § 134 from a rejection of claims 1,
2, 4-7, 9-12, 14-17, and 19-23. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

THE INVENTION
Appellants’ invention is directed to a memory system and, more
particularly, to a non-volatile memory system. (Spec. 1, ll. 2-3.)
Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. A method for fabricating a memory cell system, said method
comprising:
forming a first insulator layer over a semiconductor
substrate;
forming a charge trap layer over the first insulator layer;
forming a second insulator layer over the charge trap
layer;
forming a top blocking intermediate layer over the
second insulator layer by nitriding a top portion of the second
insulator layer; and
forming a contact layer over the top blocking
intermediate layer.
(Appeal Brief, Claims Appendix1 16.)

THE REJECTION
The Examiner rejected claims 1, 2, 4-7, 9-12, 14-17, and 19-23 under
35 U.S.C. §103(a) as unpatentable over Bhattacharyya (US 2006/0261401
A1, published November 23, 2006) in view of Jang et al. (US 2006/0008997

1 Appeal Brief filed January 23, 2009, hereinafter “App. Br.” and Claims
App’x, respectively.
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A1, published January 12, 2006). (Examiner’s Answer, dated May 6, 2009,
“Ans.” 3-6.)
ISSUE
The Examiner found that Bhattacharyya discloses a method of
fabricating a memory cell system comprising: forming a first insulator layer
over a semiconductor substrate, forming a charge trap layer over the first
insulator layer, and forming a contact layer over a top blocking intermediate
layer. (Ans. 4.) The Examiner found, however, that Bhattacharyya “does
not appear to explicitly disclose forming a second insulator layer over the
charge trap layer and forming a top blocking intermediate layer over the
second insulator layer by nitriding a top portion of the second insulator
layer.” (Ans. 4.)
The Examiner found that Jang discloses forming a second insulator
layer over a charge trap layer and forming a top blocking intermediate layer
over the second insulator layer by nitriding a top portion of the second
insulator layer in order to improve data retention. (Ans. 4.) The Examiner
determined it would have been obvious to one of ordinary skill in the art at
the time the invention was made to have formed a second insulating layer
and nitrided its top to form a top blocking intermediate layer in the device of
Bhattacharyya in order to improve data retention. (Ans. 4.)
Appellants contend that the problems addressed by Bhattacharyya and
Jang are different from the problems addressed by Appellants. (App. Br. 7-
13.) Particularly, Appellants contend that Appellants’ problem was directed
to enhancing erase speed and erase saturation in a charge trapping memory
cell by inhibiting back-gate injection into the trapping layer from the control
gate. (App. Br. 7, 13.) Appellants argue that Bhattacharyya is directed to
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solving a different problem, i.e., problems relating to migration of charge
carriers to and from a floating gate, through a tunneling insulator layer
formed adjacent to the floating gate. (App. Br. 8-9.) Because Bhattacharyya
is directed to what Appellants describe as a “different problem,” Appellants
argue that it is not surprising that Bhattacharyya does not disclose the
method recited in the claims, and that a skilled artisan would not have
looked to the concepts disclosed in Bhattacharyya to solve the problem faced
by Appellants. (App. Br. 8, 13-14.)
Likewise, Appellants argue that one of ordinary skill in the art would
not look to Jang to solve the problem faced by Appellants because Jang is
also directed to a different problem, i.e., improving data retention by
inhibiting leakage current; and further, that the teaching of Jang is directed
to a structurally distinct and alternative memory cell architecture (i.e., a
floating gate memory cell) from that taught by Appellants. (App. Br. 9-10,
13.) Appellants also argue that “even if it were to be acknowledged . . . that
it is obvious to form a second insulating layer and to nitride its top portion in
order to improve data retention, as is asserted by the Examiner [(see Ans.
4)], that does not render it obvious to use the same procedure in order to
increase erase speed.” (App. Br. 11.)
Lastly, Appellants contend that “the layer of material having both a
high dielectric constant and a large energy gap, required by Jang to be
formed between the floating gate and the control gate, is absent from the
structure disclosed and claimed by Applicants,” yet “that element in Jang
appears to be an essential component of the disclosed invention, and its
omission runs counter to the teaching of Jang.” (App. Br. 12-13.)
Thus, the dispositive issue on appeal is:
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Whether the Examiner erred in determining that it would have been
obvious to form the nitrided insulator layer of Jang over the charge-trapping
layer of the memory cell of Bhattacharyya?

PRINCIPLES OF LAW
“The use of patents as references is not limited to what the patentees
describe as their own invention or to the problems with which they are
concerned. They are part of the literature of the art, relevant for all they
contain.” In re Heck, 699 F.2d 1331, 1332-33 (Fed. Cir. 1983) (quoting In
re Lemelson, 397 F.2d 1006, 1009 (CCPA 1968)).
As stated by the Supreme Court in KSR Int'l Co. v. Teleflex Inc., 550
U.S. 398, 420 (2007), “any need or problem known in the field of endeavor
at the time of [the] invention and addressed by the patent can provide a
reason for combining the elements in the manner claimed.” KSR instructs
that “familiar items may have obvious uses beyond their primary purposes.”
Id. at 420-421. It is not necessary that the prior art suggest the combination
for the same reason as contemplated by Appellants. In re Kahn, 441 F.3d
977, 987 (Fed. Cir. 2006).

FACTUAL FINDINGS (FF)
1. Bhattacharyya discloses that “[t]he floating node memory cell
[field effect transistor] FET operates similar to the floating gate
memory cell FET, except that the charges are stored in a non-
conductive trapping layer replacing the floating gate.” (Para.
[0028].)
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2. Bhattacharyya discloses that “[a]n ideal or universal memory
would combine the high speed, low power and effectively infinite .
. . write and erase endurance of RAM with the non-volatile long
term data retention of a non-volatile memory.” (Para. [0008].)
3. Jang discloses forming an insulator layer (420) over a floating gate
(110) and forming a nitride layer (420.1) by nitriding a top portion
of the insulator layer in order to improve data retention. (Fig. 4;
Paras. [0028], [0034].)
4. Appellants’ Specification discloses a need for a memory cell
system providing improved data retention. (Spec. 2, ll.18-21.)

ANALYSIS
We do not agree with Appellants that alleged differences in the
problems addressed by the prior art and Appellants would have deterred a
skilled artisan from combining Jang with Bhattacharyya. In making these
arguments, Appellants are improperly focusing only on one particular
problem Appellants were trying to solve, whereas “any need or problem
known in the field of endeavor” can provide a reason to combine prior art
teachings. KSR at 420. Obviousness does not require that the references be
combined for the reasons contemplated by Appellants. Id.; see also In re
Kahn, 441 F.3d at 987.
Although Appellants’ discussion of the problems solved by
Appellants’ invention centers around the need for enhancing erase speed and
erase saturation by inhibiting back-gate injection (App. Br. 7, 13),
Appellants’ Specification also describes the need for a memory cell system
providing improved data retention. (FF 4.) Bhattacharyya teaches that one
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important aspect of an ideal memory would be long-term data retention. (FF
2.) Jang teaches that data retention can be improved by forming an
insulating layer on top of a floating gate and nitriding its top portion to form
a top blocking intermediate layer. (FF 3.) Thus, despite Appellants’
argument that Bhattacharyya, Jang, and Appellants’ own invention were
directed to different problems, the prior art and Appellants were, in fact, all
concerned with improving data retention. Appellants have offered no
persuasive evidence as to why a person of ordinary skill in the art concerned
with improving data retention would not have combined the teachings of two
references both concerned with improving data retention.
We also do not agree with Appellants that the architectural differences
of Jang would have deterred a skilled artisan from combining Bhattacharyya
with Jang to arrive at Appellants’ invention. Contrary to Appellants’
assertions that one of ordinary skill in the art would not have looked to Jang
because of its architectural differences, Bhattacharyya discloses that memory
cells having a charge trapping layer or memory node operate similarly to
memory cells having a floating gate. (FF 1.)
Lastly, we are not persuaded by Appellants’ argument that the
Examiner’s obvious determination is in error because the high-k dielectric
layer of Jang is absent from the structure claimed by Appellants. The
Examiner relies on Jang for its teaching of the claimed nitrided insulator
layer, not its teaching of a high-k dielectric layer.

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CONCLUSION
The Examiner did not err in determining that it would have been
obvious to form the nitrided insulator layer of Jang over the charge-trapping
layer of the memory cell of Bhattacharyya.

DECISION
We affirm the Examiner’s rejection of claims 1, 2, 4-7, 9-12, 14-17,
and 19-23 under 35 U.S.C. §103(a) as unpatentable over Bhattacharyya in
view of Jang.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1).

AFFIRMED

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