Ex Parte WU et al

Patent Trial and Appeal Board

Jun 9, 2016

13284258 (P.T.A.B. Jun. 9, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/284,258 10/28/2011
60601 7590 06/10/2016
Muncy, Geissler, Olds & Lowe, P,C,
4000 Legato Road
Suite 310
FAIRFAX, VA 22033
FIRST NAMED INVENTOR
Hsin-YiWU
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
5442/0109PUS1 7054
EXAMINER
LABOY ANDINO, NAN A
ART UNIT PAPER NUMBER
2838
MAILDATE DELIVERY MODE
06/10/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HSIN-YI WU and CHIH-FENG HUANG
Appeal2014-004805
Application 13/284,258 1
Technology Center 2800
Before CHUNG K. PAK, LINDA M. GAUDETTE, and
CHRISTOPHER L. OGDEN, Administrative Patent Judges.
PAK, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Final Action2
rejecting claims 1 and 2. We have jurisdiction pursuant to 35 U.S.C. § 6.
We affirm.
1 Application 13/284,258 (filed October 28, 2011), claiming under 35 U.S.C. §
119 the benefit of Application 099136972 filed in Taiwan on October 28, 2010.
2 Final Action mailed May 14, 2013 ("Final Act.").
Appeal2014-004805
Application 13/284,258
fNTRODUCTION
The appealed subject matter relates to a method for generating a
current limit signal for a power converter "without sensing an input voltage
of the power converter." Spec. 4, 11. 13-15. According to the Specification,
the following descriptions accompanying Figures 3 through 5 are "preferred
embodiments of the present invention." Id. at 5, 11. 5-7. The Specification
further states that the present invention "is intended to embrace all ...
alternatives, modifications and variations that fall within the spirit and scope
thereof as set forth in the appended claims." Id. at 8, 11. 22-24.
Figure 4, which is a circuit diagram of an embodiment of a power
converter (Id. at 6, 11. 10-11 ), is reproduced below:
12
,-~-----.{ ___ _
I Np:Ns i DS Vo
Vin a-----------~- ---------: Lr.~11~~---~,
~----------------i i J--- : : I ------; .Co
lO-- L Oscil;~~~~~ L~ f _:: _____ _J "7 1
-------r--- 34;_ 11., 3f! j "'v ,---J._ ___ , .
1 ~i- I
· I Po~~~~------1 Vlirnit K rl--! S Q 1-, +-1-'1~-'',,1"_~--19 QJ
1---L_ Limiter --~l~/_,_,.,1 s1 ! ~ _1 I j / L ___ l\j : :'.!-Rs
i 1----L .. J ! T
Vcs ____ --i-.... -. --------- ---f'"- ____ '7
~ ----~····--------------~:+/ I Hi V
l_···-~·····--········-------------- ...... .
Fig. 4
In Figure 4, a power converter includes controller 10, transformer 12, power
switch Ql, and current resistor Rs. Id. at 6, 11. 10-14. Controller 10
includes power limiter 30 to determine a current limit signal Vlimit
according to current sense signal Vcs. Id. at 6, 11. 15-16. Controller 10
further includes comparator 32 to compare current sense signal V cs with
2
Appeal2014-004805
Application 13/284,258
current limit signal Vlimit to generate comparison signal Sl, and tlip-tlop
34 to determine control signal PWM according to clock CLK and
comparison signal Sl. Id. at 6, 11. 17-20.
Figure 3, which is a flowchart of a particular embodiment of a method
for generating a circuit limit signal for the above power converter according
to the present invention (Id. at 5, 11. 15-16), is reproduced below:
----··-·--------_............
Deta..'ting the current Ip of
the power switch Q 1 to obtain
a current sense signal Vcs
Cou11ti11g the time At for the current
sense signal V cs to increase
from a level Vrefl to a level Vref2
Multiplying the time .6.t by a
preset parameter K to generate
an adjust value KL\t
Adding the adjust value K6t to a
preset threshold value V c to generate
a current limit signal Vlimit
Fig. 3
..-s20
S22
-,._.,,g24
·S26
In Figure 3, in step S20, controller 10 detects the voltage across
current sense resistor Rs to detect current Ip of power switch Ql to obtain
current sense signal Vcs related to current Ip. Id. at 5, 11. 20--23.
In step S22, power limiter 30 counts the time Lit for current sense
signal Vcs to increase from level Vrefl to level Vref2. Id. at 5, 11. 23-25.
Figure 5, which is "a waveform diagram of a current sense signal to
show the times that the current sense signal [V cs] increases from a first level
3
Appeal2014-004805
Application 13/284,258
to a second level under different levels of an input voltage" (Id. at 5, 11. 21-
23), is reproduced below:
Highe>' input volmge Vinl
Vrefl -----~G.i--1
I I
I I
Lower input voltage Vin2
'--.42
i--------------· .. ··--
i I
--,------T~1 ---+-
: I I
I I:
' I'
ill
/\tl i : I !
__ J : !--+-~ -------------~
I
j··--
[~t2 1
______________ _J
Fig, 5
Figure 5 shows that "current sense signal V cs will have different slopes for
different levels of the input voltage Vin." Id. at 6, 1. 25-7, 1. 1 (emphasis
added). According to the Specification, as shown in Figure 5, for higher
input voltage Viol (waveform 40), "current sense signal Vcs increases with a
steeper slope, and hence the time Lit 1 for the current sense signal V cs to
increase from the level Vrefl to the level Vref2 is shorter." Id. at 7, 11. 1-5
(emphasis added). For a lower input voltage Vin2 (waveform 42), "current
sense signal V cs increases with a flatter slope, and hence the time L'it2 for the
current sense signal V cs to increase from the level Vrefl to the level Vref2
is longer." Id. at 7, 11. 5-8 (emphasis added).
In step S24, power limiter 30 multiplies the obtained time Lit by a
preset parameter K to generate an adjust value K x Lit. Id. at 7, 11. 15-16,
Fig. 3.
In step S26, power limiter 30 adds the adjust value K x Lit to a preset
threshold value V c to generate the current limit signal Vlimit = V c + K x Lit.
Id. at 11. 17-18, Fig. 3. Because parameter Kand threshold value Ve are
4
Appeal2014-004805
Application 13/284,258
constant, current limit signal Vlimit increases with time Lit, i.e., "for a lower
input voltage Vin2 . . . power limiter 30 provides a higher current limit
signal Vlimit, and contrarily, for a higher input voltage Viol ... power
limiter 30 provides a lower current limit signal Vlimit." Id. at 7, 1. 19--8, 1.
2, Fig. 3 (emphasis added).
Details of the appealed subject matter are recited in representative
independent claim 1, which is reproduced below from the Claims Appendix
in the Appeal Brief 3 (bracketed reference characters of preferred
embodiments of Specification Figures 3 and 4) (emphasis added):
1. A method for generating a current limit signal for a
power converter without sensing an input voltage of the power
converter, the method comprising the steps of:
(A) detecting [S20] a current [Ip] of a power switch [Ql]
of the power converter to obtain a current sense signal [Vcs];
(B) counting [S22] an input voltage dependent time [At]
for the current sense signal [V cs] to increase from a first level
to a second level; and
(C) determining [S24, S26] a current limit signal [Vlimit]
according to the input voltage dependent time [At] for limiting a
maximum value of the current [Ip] of the power switch [Ql].
In the Examiner's Answer, 4 the Examiner maintains the following
grounds of rejection, which are before us on appeal:
1. Claim 1under35 U.S.C. § 102(b) as anticipated by Yang '420 5.
3 Appeal Brief filed on October 15, 2013 ("App. Br.").
4 Examiner Answer mailed on January 2, 2014 ("Ans."). Final Act. 2-5.
5 Yang et al., United States Patent Publication No. 2008/0170420 Al; published
on July 17, 2008 ("Yang '420").
5
Appeal2014-004805
Application 13/284,258
2. Claim 2 under 35 U.S.C. § 103(a) as unpatentable over the
collective teachings of Yang '420 and Yang '6566.
DISCUSSION
Rejection 1, Anticipation by Yang '420
In rejecting independent claim 1 as anticipated by Yang '420, the
Examiner finds that Yang '420 teaches a method for generating a current
limit signal for a power converter "without sensing an input voltage of the
power converter," as illustrated in Yang '420, Figure 2, which is shown on
the following page. The Examiner finds that the Yang '420 method
comprises:
Step (A) recited in claim 1 - "current sensor resistor Rs in Fig. 2;
paragraph [0020], lines 8-11" (Final Act. 2);
Step (B) recited in claim 1 - "paragraph [0021 ]; it is clear that a time
period (Lit) can be obtained from the slope of the sense current curve and any
two sense current reference points (first and second level)" (Final Act. 2-3);
and
Step (C) recited in claim 1 -
paragraph [0023], lines 10-13; Yang teaches the generation of a
current limit signal in accordance with an input voltage
determined from a correlation with the sense current signal
slope (paragraph [0021 ], lines 2--4); as explained above it is
clear there is a time period (Lit) considered within the slope of
the sense current which correlates to the current limit signal
determination.
(Final Act. 3).
6 Yang et al., United States Patent No. 6,674,656 Bl; issued on January 06, 2004
("Yang '656").
6
Appeal2014-004805
Application 13/284,258
Yang '420, Figure 2, which is reproduced below, shows a circuit
diagram of a circuit of a power converter according to the invention of Yang
'420. Yang '420 i-f 10.
FIG. 2
The Yang '420 power converter in Figure 2 includes power transistor 20,
transformer 30, rectifier 40, capacitor 45, switching controller 50, and
resistor Rs. Yang '420 i-f 20. Transformer 30 serves as an inductance device
coupled to receive input voltage V1N. Id. Power transistor 20 is connected
serially with transformer 30 to switch transformer 30. Id. Resistor Rs
serves as a current sense circuit connected to power transistor 20 to develop
current signal V1 in response to switching current Ip of transformer 30.
Current signal V1 represents switching current h. Id.
Regarding step (A), Yang '420 describes current signal V1 that
corresponds to the "current sense signal" (V cs) recited in claim 1. Id. The
Yang '420 current signal V1 is coupled to a current-sense terminal VS of
switching controller 50 for the control and protection of the power converter.
Id. Output terminal OUT of switching controller 50 generates switching
signal Sw to control power transistor 20 for regulating the output of the
power converter in response to current signal V1 and feedback signal VFn.
7
Appeal2014-004805
Application 13/284,258
Id. Feedback signal VFn is generated at feedback terminal .FB of switching
circuit 50 for the feedback regulation in response to the output of the power
converter. Id. The energy of transformer 30 is transferred to output voltage
Vo of power converter through rectifier 40 and capacitor 45. Id.
Regarding step (B), Yang '420 (id. i-f 21, emphasis added) states that
switching controller 50 [in Fig. 2] detects the input voltage VIN
for the protections [sic] of the power converter. The input
voltage V1N is detected by sensing a slope of the switching
current Ip . . . [which] is produced in response to the level of
the input voltage VIN,
as shown in Yang '420, Figure 3. Yang '420, Figure 3, which shows
switching current waveforms, (Yang '420 i-f 11) is reproduced below:
Sw_J
I I I
--i i--- TON I
"~t ~ =1T~-. ~
I,--1#111 ( ~I ---~'*4~-1 I I I
33 -1 I- T
FIG. 3
According to Yang '420, "[fJor example, the slopes 31, 32, and 33 are
generated in response to the input voltage V1N1, V1N2 and V1N3, respectively.
The level of the input voltage is VIN> V1N2 > V1N3". Id. at i-f 21 (emphasis
added). When switching signal Sw is turned on, switching current Ip is
generated accordingly,
(l)
. , a!xL,,
~·f-.:=--•.. , !J.T
(2)
8
Appeal2014-004805
Application 13/284,258
where Lp is the inductance of the primary winding of the transformer, ToN is
"on time of the switching signal Sw." Id. at i-fi-121, 22 (emphasis added).
Regarding step (C), in the words of Yang '420 (id. i123), "VIN-circuit
200 [in the circuit diagram of switching controller 50 shown in Fig. 4,
reproduced below] generates a control signal ENB, a current-limit signal
VM and a blanking adjustment signal Vn in response to the input-voltage
signal V v for power converter protections [sic]" (emphasis added). Yang
'420, Figure 4, which shows a circuit diagram of switching controller 50 (Id.
at i-f 12), is reproduced below:
FrG.4
The Yang '420 switching controller 50 in Figure 4 includes switching circuit
60, which generates switching signal Sw in response to oscillation signal
IPS. Id. at i123. Controller 50 further comprises oscillation circuit 100 and
VIN-circuit 200. Id. Oscillation circuit 100 generates oscillation signal IPS
and timing signals S1 and S2. Id. Timing signals S1 and S2 serve as sample
signals outputted to VIN-circuit 200. VIN-circuit 200 receives current signal
V1 to produce input-voltage signal Vv (shown in Yang '420, Fig. 10) "in
accordance with the slope of the current signal V1." Id. (emphasis added).
9
Appeal2014-004805
Application 13/284,258
As discussed supra, the slope of current V1 is the slope of switching current
Ip described in Figure 3. Id. VIN-circuit 200 then generates current-limit
signal VM, as well as control signal ENB and blanking adjustment signal Vn,
in response to input-voltage signal Vv for power converter protection. Id.
Switching circuit 60 includes comparator 62 and flip-flop 70. Id. at i-f 26.
Comparator 62 compares current limit signal VM to current sense V1 to limit
the maximum switching current h. Id. Flip-flop 70 generates switching
signal Sw through AND gate 75. Id. at i-f 24. AND gate 75 receives
oscillation signal IPS from oscillation circuit 100 to limit the "maximum on
time of the switching signal Sw." Id. (emphasis added).
Appellants do not dispute the Examiner's findings that Yang '420
teaches a method for generating a current limit signal for a power converter
"without sensing an input voltage of the power converter," as shown in Yang
'420, Figure 2. Compare Final Act. 2 with App. Br. 8-9. Nor do
Appellants dispute the Examiner's finding that Yang '420 teaches step (A)
as recited in claim 1. Compare Final Act. 2 with App. Br. 8-9. Nor do
Appellants dispute the Examiner's finding that Yang '420 determines a
current limit signal "for limiting a maximum value of the current of the
power switch." Compare Final Act. 3 with App. Br. 8-9.
Rather, Appellants urge that Yang '420 does not disclose or suggest
"to count the period of time for the current sense signal V cs rising from a
first level to a second level", as set forth in step (B) in claim 1. App. Br. 8.
In particular, according to Appellants (id.), in Yang '420, "the time period Lit
that is used to guess the slope of the current sense signal V cs is a preset
constant, regardless of the current sense signal V cs and the input voltage
10
Appeal2014-004805
Application 13/284,258
Vin, since it is the time difference between the two preset time points."
Appellants urge that in Figure 3, Yang '420
determines the slopes 31-33 of the switching current Ip
according to the variation of the switching current Ip during a
preset time period ~t=Ton ... since the time period ~t ... is
fixed (Ton) and does not change with the input voltage VIN, it
does not disclose the input voltage dependent time as recited in
claim 1.
Id. at 8-9. Notwithstanding Appellants' arguments to the contrary, Yang
'420's determination of the slope of switching current Ip, as shown in Yang
'420, Figure 3, is within the step (B) process limitations recited in claim 1.
As shown in Yang '420, Figure 3, the Ip current level is dependent on the
time the switching signal Sw is on (T oN) and on the input voltage V1N.
Although the Yang '420 time T oN may be fixed, when the switching signal
Sw is turned on for time T oN, time is being counted from time zero until the
time reaches ToN. Yang '420 i-fi-121, 22 and Fig. 3. As discussed supra, in
Yang ;420, Figure 4, in switching controller 50, flip-flop 70 generates
switching signal Sw. In addition, as correctly found by the Examiner, in
Yang '420, Figure 3, the time period ~t (i.e., ToN) is "associated to the
switching current lp rising from a first level to a second level." Ans. 3. Put
another way, in Yang '420, the Ip current level increases from a first level
value at time zero to a second level value at time ToN. Yang '420 Fig. 3. As
noted supra, the Yang '420 switching current Ip represents current signal V1,
which meets the "current sense signal" (V cs) recited in claim 1. Thus, the
Yang '420 Ip first and second levels meet the "current sense signal" first
level and second level recited broadly in claim 1.
Moreover, as determined by the Examiner, claim 1 does not recite that
the time being counted in step (B) changes with input voltage, as urged by
11
Appeal2014-004805
Application 13/284,258
Appellants. Ans. 4. Nor does claim 1 recite that "the first and second sense
current levels are fixed/preset values." Id. Appellants have not directed our
attention to any disclosure in the Specification that defines the time being
counted in step (B) as changing with input voltage, as urged by Appellants.
App. Br. 8-9. Nor have Appellants directed our attention to any disclosure
in Specification that defines the step (B) "first level" and "second level" as
being preset values. Id. Although in the Specification, Figures 3 and 5, the
current sense signal first and second levels are described as preset references
levels, Vrefl and Vref2, as noted supra, the Specification states the
descriptions accompanying Figures 3 and 5 are "preferred embodiments of
the present invention" (Spec. 5, 11. 5-7) and that the present invention "is
intended to embrace all ... alternatives, modifications and variations that
fall within the spirit and scope thereof as set forth in the appended claims"
(Spec. 8, 11. 22-24). On this record, Appellants have not proffered any
reason to import the description of preferred embodiments in the
Specification into the claims. In re Van Geuns, 988 F.2d 1181, 1184 (Fed.
Cir. 1993) ("[L ]imitations are not to be read into the claims from the
specification.").
On this record, Appellants have not identified harmful error in the
Examiner's findings that Yang '420 counts the time the input voltage VIN is
on for the Ip current level to increase from a first level at time zero to a
second level at time ToN- Accordingly, we find that a preponderance of the
evidence supports the Examiner's finding that Yang '420 describes step (B)
recited in claim 1.
Appellants further urge that because Yang '420 does not teach step
(B), Yang '420 does not teach or suggest "determining a current limit signal
12
Appeal2014-004805
Application 13/284,258
according to the input voltage dependent time for limiting a maximum value
of the current of the power switch" as set forth in step (C) of claim 1. App.
Br. 8. Appellants traverse the Examiner's position (Final Act. 5) that
because Yang '420
teaches generation of a current limit signal in accordance with
an input voltage determined from a correlation with the sense
current signal slope ... it is clear that a time period Lit is
considered within the slope of the sense current which
correlates to the current limit signal determination.
App. Br. 9. Appellants urge that Yang '420, paragraph 32, "teaches to
generate a slope signal VSD that is directly proportional to the input voltage
VIN ... [which] is equal to the variation Lil of the switch current Ip during
the time period Lit." Id. Appellants urge that according to Yang '420
equation (2) in paragraph 21, "the time period Lit must be a fixed constant
when the variation Lil of the switch current Ip is directly proportional to the
input voltage VIN." Id. Appellants conclude that "the time period Lit of
Yang [']420 does not change with the input voltage VIN and is not
considered within the slope of the sense current which correlates to the
current limit signal determination." Id.
Appellants' arguments are not persuasive. As we have discussed
above, Yang '420 discloses step (B). Moreover, contrary to Appellants'
arguments, Yang '420, paragraph 32, does not disclose that the slope signal
V sD is "directly proportional to the input voltage VIN." Rather, according to
Yang '420, paragraph 32,
[t]he slope signal VsD is ... correlated to the slope of the
current signal Vi. The level of the slope signal V sD is corrected
to the input voltage VIN of the power converter. The slope
signal V sD is increased in response to the increase of the input
voltage VIN
13
Appeal2014-004805
Application 13/284,258
(emphasis added). As shown in Yang '420, Figure 3, the slope of switching
current Ip (which represents current signal V1) increases with the input
voltage V1N. As discussed supra, as shown in Yang '420, Figure 3, the Ip
current level increases from a first level value at time zero to a second level
value at the time the switching signal Sw is on (T oN). Thus, as correctly
found by the Examiner (Ans. 3), the slope of switching current Ip is
dependent on the time (Lit) the switching signal Sw is on. As also found by
the Examiner (id.), in Yang '420, Figure 4, VIN-circuit 200 receives current
signal V1, and then generates current-limit signal VM. Further, as discussed
supra, in describing Figure 4, Yang '420 discloses that VIN-circuit 200
receives current signal V1 to produce input-voltage signal Vv in accordance
with the slope of the current signal V1, i.e., the slope of switching current Ip
as described in Figure 3. Finally, as discussed supra, claim 1 does not recite
that the time being counted in step (B), Lit, changes with input voltage.
Thus, on this record, Appellants have not identified harmful error in
the Examiner's findings that Yang '420 generates a current limit signal VM
in accordance with the slope of current signal VIN as taught by Yang '420,
which in tum is determined from the time period Lit the input voltage V1N is
on, as described supra. Accordingly, we find that a preponderance of
evidence supports the Examiner's finding that Yang '420 describes step (C).
Accordingly, Rejection 1 is affirmed.
Rejection 2, Obviousness over the collective teachings
of Yang '420 and Yang '656
In rejecting claim 2, which depends from claim 1, the Examiner finds
that Yang '420 fails to disclose that its current limit determination step (C)
14
Appeal2014-004805
Application 13/284,258
comprises the steps recited in claim 2. Final Act. 3. To account for the
differences between Yang '420 and the claimed invention in claim 2, the
Examiner finds that Yang '65 6 teaches the steps recited in claim 2 for
determining the current limit signal. Id. at 4 (citing Yang '656, Fig. 2,
elements 80, 300; col. 4, formula 8).
Appellants urge that "Yang [']656 fails to disclose the steps Band C
recited in claim 1 ... and thus fails to cure the deficient teachings of Yang
[']420, at least in regard to claim 1." App. Br. 10. However, as we have
discussed supra, a preponderance of the evidence supports the Examiner's
findings that the method for generating a current limit signal taught by Yang
'420 comprises steps (A), (B), and (C) as recited in claim 1.
Accordingly, Rejection 2 is affirmed.
DECISION
In view of the foregoing, we AFFIRM the rejections of claim 1 under
35U.S.C. § 102(b)andofclaim2under35U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
15