Ex Parte WISE

Board of Patent Appeals and Interferences

Jul 22, 2004

09126171 (B.P.A.I. Jul. 22, 2004)

1
The opinion in support of the decision being entered today was not written for
publication and is not binding precedent of the Board.
Paper No. 18

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________
Ex parte ADRIAN PHILIP WISE
_____________
Appeal No. 2003-1544
Application No. 09/126,171
______________
ON BRIEF
_______________
Before HAIRSTON, KRASS, and FLEMING, Administrative Patent Judges.
KRASS, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal from the final rejection of claims 1-19.
The invention is directed to the decoding of video data. In particular, the
invention is said to improve upon the prior art depicted in Figure 1 by providing an on-
chip block-to-raster buffer connected to the video decoder and eliminating memory
region 12 for storing a decoded B-frame.
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Representative independent claim 1 is reproduced as follows:
1. A video decoder comprising:
a memory for storing a plurality of anchor frames suitable for
decoding a plurality of intermediate frames; and
a buffer independent of the memory for holding intermediate frame
data for display, characterised in that the video decoder is operable in first
and second modes of operation,
wherein in a first mode of operation a picture is encoded as a
single frame and the video decoder decodes the single frame twice
wherein (i) in a first decoding a set of lines of a first field of the single
frame are provided to the buffer for display and (ii) in a second decoding a
set of lines from a second field of the single frame are provided to the
buffer for display; and
wherein in a second mode of operation in which two consecutive
field pictures of a frame are decoded, (i) a first field picture of the two
consecutive field pictures is decoded and provided to the buffer for display
and then (ii) a second field picture of the two consecutive field pictures is
decoded and provided to the buffer for display.
The examiner relies on the following references:
Hoogenboom 5,717,461 Feb. 10, 1998
Schoner et al. (Schoner) 5,903,282 May 11, 1999
(filed Jul. 28, 1997)
Claims 1-19 stand rejected under 35 U.S.C. §103 as unpatentable over
Hoogenboom and Schoner.
Reference is made to the briefs and answer for the respective positions of
appellant and the examiner.
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OPINION
With regard to independent claims 1, 9 and 15, the examiner contends that
Hoogenboom discloses a decoding process, in Figure 2,
to decode data in a frame order with display of the data in a field
order in a first mode of operation to decode the frame, wherein the
decoding of half the B-frame in a frame order that involves the
processing of one-half of field one of the B-Frame and one-half
of field two of the B-frame. One-half of the first field is equivalent
to one quarter of the whole frame (col. 9, lines 23-38), and second
mode of operation in which two consecutive fields, where the display
of the first field of each B-frame would commence before that field
has been entirely decoded. Thus, it is possible to write into the buffer
lines vacated by display of the first half of the first B-frame field, when
decoding the second half of that field (col. 8, lines 32-39; fig. 4).
Hoogenboom further suggests the decoder to decode two consecutive
field pictures, wherein a frame a first field is decoded and displayed and
a second field is decoded and displayed (col. 9, lines 39-50) (answer-page 3).
The examiner further notes, with regard to independent claims 14 and 19,
Hoogenboom further discloses DRAM mapping for a digital video
decompression processor (fig. 1) for decompressing a digital signal
as MPEG-2 standard, including a memory DRAM (fig. 2) for storing
a plurality of anchor frames (col. 7, lines 44 through col. 8, lines 1-39),
and the decoder (48 of fig. 1) for decoding intermediate frames,
including buffer means (30 of fig. 1) for holding intermediate frame
data for display (col. 6, lines 43-57), wherein the buffer means for
distributing incoming data to any available memory location in
buffer, the address of the memory location being stored (col. 6, line 43
through col. 7, lines 1-25). See also col. 3, line 31 through col. 5,
lines 1-21. (answer-page 4).
The examiner’s analysis finds that Hoogenboom does not specifically disclose a
single frame being decoded twice, as specified in claims 1, 9 and 15, and does not
disclose a pointer table as part of the buffer, as in claims 14 and 19.
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The examiner then turns to Schoner for a teaching of a
decoder (114 of fig. 8) for decoding a B-frame that is considered
as a single frame in a first decoding set of lines that are considered
as odd lines of a first field (odd field) and a second decoding set of
lines that are considered as even lines of a second field (even field)
(col. 9, lines 60 through col. 10, lines 1-9), and a pointer table in
FIFO Buffers (116 of fig. 8) for distributing incoming data to any
available memory location in buffer, the address of the memory
location being stored in the pointer table. (answer-page 5).
The examiner then concludes, from these teachings of Hoogenboom and
Schoner, that it would have been obvious to incorporate the decoder and pointer table
of Schoner into the decoding system of Hoogenboom “for [the] same purpose of
decoding the single frame twice and pointer is distributing incoming data to any
available memory location FIFO buffers” (answer-page 5). The examiner suggests that
the artisan would have been led to make this combination so as to “reduce the memory
requirements of the decoder as much as possible to reduce its size and cost” (answer-
page 5), citing column 5, lines 28-30, of Schoner.
Appellant takes the position that the examiner has failed to present a prima facie
case of obviousness in that there is no reasonable expectation of success for the
suggested combination. In particular, appellant contends that no evidence has been
provided for where in the processor 20 of Hoogenboom the decoder 114 and buffer 116
of Schoner would be inserted.
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Moreover, asserts appellant, even if decoder 114 and buffer 116 of Schoner
could somehow be incorporated into Hoogenboom, the modified processor 20 would
be unable to display video data. In contrast thereto, argues appellant, instant claim 1
requires a buffer independent of a memory for holding intermediate frame data for
display and instant claim 15 requires a buffer system independent of a memory coupled
to the decoder and which holds data of the intermediate frames for display. Since the
proposed combination would not result in any display capability, appellant argues, the
suggested combination of references is improper for a showing of obviousness of the
instant claimed subject matter.
Appellant argues that the Hoogenboom and Schoner teachings conflict in the
area of reconstructing the decoded video for display but that even if the combination is
made, the claimed subject matter of a buffer/buffer system independent of a memory
and a first mode of operation where a picture is encoded as a single frame and a
decoder decodes the single frame twice is still not suggested by the combination of
references.
This is so, according to appellant, because Hoogenboom teaches that the
anchor frames 70 and 76 and the decoded B-fields 80 and 82 are all stored in a DRAM
22 under the control of a memory manager 30; and Schoner teaches that two anchor
frames and a portion of a B-frame are stored in a memory 102. Appellant contrasts
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these teachings with instant claim 1 which provides for a buffer “independent of a
memory” for holding intermediate frame data; and instant claim 15 which provides for a
buffer system “independent of a memory” coupled to a decoder and which holds data of
the intermediate frames. Appellant asserts that Hoogenboom and Schoner are silent
with regard to a buffer or buffer system independent from the DRAM 22 or memory 102
for holding the decoded B-fields.
Moreover, argues appellant, whereas instant claims 1 and 15 provide a first
mode of operation where a picture is encoded as a single frame and the decoder
decodes the single frame “twice,” Hoogenboom teaches that B-frames can be decoded
on a frame basis into a first field and a second field and Schoner teaches that the
bitstream decoder 114 decodes a next frame after reaching the end of a current frame.
Appellant stresses that decoding two fields of a single frame is not the same as
decoding the single frame twice, and that neither of the references, taken alone or in
combination, teaches or suggests decoding a frame twice, as required by the instant
claims.
We have reviewed the references, as well as the arguments of both appellant
and the examiner and we have concluded that appellant is correct in his assessment
that the examiner has not set forth a prima facie case of obviousness.
Each independent claim requires, inter alia, that there be a buffer “independent”
of the memory for holding intermediate frame data for display. In addition, independent
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claims 1, 9 and 15 require that a single frame is decoded twice.
We agree with appellant that the cited references do not appear to teach or
suggest at least these two claimed features.
The examiner relies on Hoogenboom’s DRAM 22 being “independent” from
“memory” 30 as a teaching of the independent memory limitation. However, it is clear
from Hoogenboom’s disclosure, e.g., column 6, line 13, that element 30 is a “memory
manager,” and not a memory, as alleged by the examiner. Moreover, there is no
evidence in Hoogenboom that there is a buffer that holds intermediate frame data for
display and that it is this buffer which is “independent” of the memory. If it is
Hoogenboom’s DRAM 22 which is relied on by the examiner as holding intermediate
frame data for display, then there is no evidence that this DRAM is independent of any
memory in Hoogenboom.
Further, to the extent that the examiner appears to rely some on Schoner’s FIFO
pointers and external memory 102 for this claim limitation, the FIFO pointers point to
addresses in the external memory and cannot said to be “independent” of that memory.
With regard to a single frame being decoded twice, the examiner relies on
Hoogenboom, at column 9, lines 23-38. The examiner alleges that Hoogenboom’s
decoder 20 has a decoding mode to decode a frame one-half of field one of the B-
frame and one-half of field two of the B-frame, “so this means that B-frame would be
decoded two times” (answer-page 6).
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However, reading a bit further in the reference, past the cited portion, reveals
that appellant’s explanation, at pages 2-3 of the reply brief is correct:
Hoogenboom teaches decoding a B-frame in a frame order.
Hoogenboom teaches storing decoded “field one” data in buffer
80 and decoded “field two” data in buffer 82. Half way through
decoding the B-frame, the buffer 80 becomes full. Therefore, the
system starts to display the decoded frame and thereby starts to empty
the buffer 80. As buffer 80 is being emptied for display, decoding
of the B-frame continues with the now emptying buffer 80 continuing
to accept the decoded “field one” data and the larger buffer 82 continuing
to accept the decoded “field two” data. After the B-frame has been decoded
once, the system finishes displaying the “field one” data from the buffer 80
and then displays the “field two” data from the buffer 82. As a result, buffer
80 is used twice during one decode of the B-frame. Hoogenboom does not
appear to teach or suggest decoding the B-frame a second time because after
the first decode, all of the decoded field information has either been displayed
from buffer 80 and/or is available for display in buffer 80 and buffer 82.
We also agree with appellant that Schoner also does not appear to teach the
decoding of a B-frame twice, as claimed. The examiner relies on column 9, line 60
through column 10, line 9, of Schoner and contends that Schoner decodes a B-frame in
a first decoding of a set of odd lines of a first field and a second decoding of a set of
even lines of a second field. Accordingly, alleges the examiner, since the first field and
second field are in a frame, the decoder “would obviously decode the frame twice”
(answer-page 6).
We agree with appellant that the placing of decoded odd lines and decoded
even lines into two different memory blocks (which is taught by the cited portion of
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Schoner) does not teach or suggest decoding the B-frame twice, as required by some
of the instant claims.
Since the examiner has not convincingly shown that Hoogenboom and/or
Schoner disclose, either separately or in combination, at least the independent memory
and the double decoding features of the instant claims, we will not sustain the rejection
of any of the claims under 35 U.S.C. §103.
The examiner’s decision rejecting claims 1-19 under 35 U.S.C. §103 is reversed.
REVERSED
KENNETH W. HAIRSTON )
Administrative Patent Judge )
)
)
)
) BOARD OF PATENT
ERROL A. KRASS ) APPEALS
Administrative Patent Judge ) AND
) INTERFERENCES
)
)
)
MICHAEL R. FLEMING )
Administrative Patent Judge )
EAK/vsh
Appeal No. 2003-1544
Application No. 09/126,171
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