Ex Parte Wingard et al

Patent Trial and Appeal Board

Sep 28, 2016

12145257 (P.T.A.B. Sep. 28, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/145,257 06/24/2008 Drew E. Wingard
34284 7590 09/30/2016
Rutan & Tucker, LLP
611 ANTON BL VD
SUITE 1400
COST A MESA, CA 92626
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
026517-0055P 2985
EXAMINER
MERCADO, RAMON A
ART UNIT PAPER NUMBER
2132
NOTIFICATION DATE DELIVERY MODE
09/30/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
patents@rutan.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DREW E. WINGARD, CHIEN-CHUN CHOU, STEPHEN W.
HAMIL TON, IAN ANDREW SW ARBRICK, and VIDA V AKILOTOJAR
Appeal2015-000606
Application 12/145,257 1
Technology Center 2100
Before ALLEN R. MacDONALD, KEVIN C. TROCK, and
JOSEPH P. LENTIVECH, Administrative Patent Judges.
TROCK, Administrative Patent Judge.
DECISION ON APPEAL
Introduction
Appellants seek review under 35 U.S.C. § 134(a) from the Examiner's
non-final rejection of claims 1-20. We have jurisdiction under 35 U.S.C.
§ 6(b ).
We AFFIRM.
1 Appellants indicate the Real Party in Interest is Sonics, Inc. App. Br. 3.
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Application 12/145,257
Invention
The claimed invention relates to an interconnect for an integrated
circuit communicating transactions between initiator Intellectual Property
(IP) cores and multiple target IP cores coupled to the interconnect. Abstract.
Exemplary Claim
Exemplary claim 1 is reproduced below with disputed limitations
emphasized:
1. An interconnect for an integrated circuit to communicate
transactions between one or more initiator Intellectual Property (IP) cores and
multiple target IP cores coupled to the interconnect, wherein the interconnect
implements an address map with assigned address for target IP cores in the
integrated circuit to route the transactions between the target IP cores and
initiator IP cores in the integrated circuit and a first aggregate target of the
target IP cores includes two or more memory channels that are interleaved in
an address space for the first aggregate target in the address map, where each
memory channel is divided up in defined memory interleave segments and
then interleaved with memory interleave segments from other memory
channels, wherein the address map is divided up into two or more regions,
each interleaved memory interleave segment is assigned to at least one of
those regions and populates the address space for that region, the address map
is configurable, the address map has configurable parameters that can be set
for each region to flexibly support a configuration of the first aggregate target
that is dynamically changeable, and the configurable parameters, associated
with the regions and memory interleave segments, are configurable to
reconfigure memory channel-to-region assignments.
Rejection
Claims 1-20 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Wang et al. (US 6,466,825 Bl; issued Oct. 15, 2002),
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Application 12/145,257
Hsieh et al. (US 7,552,292 B2; issued June 23, 2009), and Cho et al. (US
6,877,076 Bl; issued Apr. 5, 2005).
ANALYSIS
We have reviewed the Examiner's rejections and the evidence of
record in light of Appellants' arguments that the Examiner has erred. We
disagree with Appellants' arguments and conclusions. We adopt as our own,
( 1) the findings and reasons set forth by the Examiner in the Office Action
from which this appeal is taken and (2) the findings and reasons set forth in
the Examiner's Answer. We concur with the conclusions reached by the
Examiner and further highlight specific findings and argument for emphasis
as follows.
Independent Claim 1
Appellants contend the Examiner erred in rejecting independent claim
1 because the combination of Wang, Hsieh, and Cho fails to teach or suggest
[a Jn interconnect ... wherein the interconnect implements an
address map ... the address map has configurable parameters
that can be set for each region to flexibly support a
configuration of the first aggregate target that is dynamically
changeable, and the configurable parameters, associated with
the regions and memory interleave segments, are configurable
to reconfigure memory channel-to-region assignments,
as recited in independent claim 1. App. Br. 7-18; Reply Br. 4--12.
Appellants argue Hsieh fails to teach or suggest configurable
parameters such that the aggregate target is dynamically changeable and
configurable parameters associated with the regions and memory interleave
segments to reconfigure memory channel-to-region assignments. App. Br.
7-14; Reply Br. 10-12. Appellants also argue Cho fails to teach or suggest
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a memory controller and associated address map located within an
interconnect and configuration parameters set or otherwise configurable for
memory channel-to-region assignments. App. Br. 8-11, 14--18; Reply Br.
4--9. Appellants argue none of the cited references teach or suggest logic
being located in an interconnect component. Reply Br. 7, 8.
The test for obviousness is what the combined teachings of the
references would have suggested to those of ordinary skill in the art. In re
Keller, 642 F.2d 413, 425 (CCPA 1981). Accordingly, one cannot show
non-obviousness by attacking references individually where, as here, the
rejections are based on combinations of references. Id. Each reference cited
by the Examiner must be read, not in isolation, but for what it fairly teaches
in combination with the prior art as a whole. See In re Merck & Co., Inc.,
800 F.2d 1091, 1097 (Fed. Cir. 1986).
Here, the Examiner finds, and we agree, the combination of Wang,
Hsieh, and Cho teaches an
address map is divided up into two or more regions [group X and
group Y represent two different regions, each with the addresses
from 0001 to 2048 and 2049 to 3072 respectively, c4 L33-38 on
Hsieh], each interleaved memory interleave segment is
assigned to at least one of those regions and populates the
address space for that region [Fig. 3B shows the mapping of
the regions to the channels and the interleaving between the
channels as well, c4 L33-38 on Hsieh], and that the address map
is configurable [through configuration registers, c6 L30-40
on Cho], the address map has configurable parameters that
can be set for each region to flexibly support a configuration
of the first aggregate target that is dynamically changeable,
and the configurable parameters, associated with the regions
and memory interleave segments, are configurable to
reconfigure memory channel-to-region assignments [the
values stored in Cho's configuration registers determine the
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Application 12/145,257
mapping of aaaress ranges for the channels, c7 L40-50; i.e.
channel-to-region assignments]; as claimed.
Ans. 15, 16. See also Non-Final Act. 5-8.
With respect to Appellants' argument that Hsieh fails to teach or
suggest configuration parameters that are dynamically changeable, the
Examiner finds, and we agree, Appellants' Specification explains that the
parameters in each region may be configured when the hardware is built.
Ans. 14 (citing Spec. i-f 59). The Specification also explains that the
configurable parameters may include "[b]ase_address of the region
parameter; region_size parameter; address_space parameter; an association
with a target parameter; an interleave_size_parameter; and an active_targets
parameter." Id. (citing Spec. i-f 36). Therefore, in light of the Specification's
explanation, we agree with the Examiner that Hsieh teaches configuration
parameters that are dynamically changeable. Ans. 14, 15.
With respect to Appellants' argument that none of the cited art teaches
or suggests "logic being locatable in the interconnect component" (Reply Br.
8), we note that claim 1 recites "wherein the interconnect implements an
address map." Claim 1 does not recite "wherein an address map is located
(or locatable) in an interconnect." Appellants' Specification does not
provide a special definition for the term "implements". In the context of
claim 1 and the Specification, the term "implement" is used as a verb, whose
plain and ordinary meaning is "to make (something) active or effective."
See e.g. Merriam-Webster's online dictionary. In contrast, Appellants'
Specification uses different terms when describing the physical location of
the logic. See e.g. Spec. i-f 83 ("The interconnect 658 implements flow
control logic internal to the interconnect 618 itself . .. '') (emphasis added).
Appellants could have, but did not, limit the physical location of the logic
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Application 12/145,257
recited in claim 1 internally to the interconnect. Accordingly, Appellants'
argument that claim 1 requires that the address map or logic be located in the
interconnect itself is an unreasonable interpretation of claim 1 in light of the
Specification. We, therefore, agree with the Examiner's interpretation of
claim 1. See Ans. 17, 18.
Therefore, we are not persuaded by Appellants' arguments that the
Examiner erred in finding the combination of Wang, Hsieh, and Cho teaches
or suggests
[a Jn interconnect ... wherein the interconnect implements an
address map ... the address map has configurable parameters
that can be set for each region to flexibly support a
configuration of the first aggregate target that is dynamically
changeable, and the configurable parameters, associated with
the regions and memory interleave segments, are configurable
to reconfigure memory channel-to-region assignments,
as recited in independent claim 1. Accordingly, we sustain the Examiner's
rejection of claim 1under35 U.S.C. § 103(a).
Claims 2-20
Appellants have not presented separate, substantive arguments with
respect to claims 2-20. See App. Br. 7-18. Rather, Appellants state that for
purposes of this appeal, claims 1-20 stand or fall together. App. Br. 7.
Because we have sustained the Examiner's rejection of independent claim 1,
we, therefore, sustain the Examiner's rejections of claims 2-20 under
35 U.S.C. § 103(a). Non-Final Act. 8-16. See 37 C.F.R. § 41.37(c)(l)(iv);
In re Lovin, 652 F.3d 1349, 1356 (Fed. Cir. 2011) ("We conclude that the
Board has reasonably interpreted Rule 41.3 7 to require applicants to
articulate more substantive arguments if they wish for individual claims to
be treated separately.").
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Application 12/145,257
DECISION
We AFFIRM the Examiner's rejections of claims 1-20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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