Ex Parte Williams

Board of Patent Appeals and Interferences

Feb 26, 2010

11273825 (B.P.A.I. Feb. 26, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte TIMOTHY JOHN WILLIAMS
____________

Appeal 2009-001569
Application 11/273,825
Technology Center 2800
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Decided: February 26, 2010
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Before JOSEPH F. RUGGIERO, KARL D. EASTHOM, and ELENI
MANTIS MERCADER, Administrative Patent Judges.

RUGGIERO, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Final Rejection
of claims 1, 2, 8-12, and 14-17. Claims 3-7, 13, and 18-20 have been
indicated by the Examiner to contain allowable subject matter if rewritten in
independent form. We have jurisdiction under 35 U.S.C. § 6(b).
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We affirm.
Rather than reiterate the arguments of Appellant and the Examiner,
reference is made to the Brief (filed November 5, 2007), the Answer (dated
April 9, 2008), and the Reply Brief (filed April 22, 2008) for the respective
details. Only those arguments actually made by Appellant have been
considered in this decision. Arguments which Appellant could have made
but chose not to make in the Briefs have not been considered and are
deemed to be waived (see 37 C.F.R. § 41.37(c)(1)(vii) (2008)).

Appellant’s Invention
Appellant’s invention relates to an over-voltage tolerant input circuit
which includes an N-well bias circuit electrically coupled to the pad, and a
current block circuit electrically coupled to the N-well bias circuit. (See
generally Spec. 4:3-14).
Claim 1 is illustrative of the invention and reads as follows:
1. An over-voltage tolerant input circuit, comprising:
a pad;
a N-well bias circuit electrically coupled to the pad; and
a current block circuit electrically coupled to the N-well bias circuit.

The Examiner’s Rejection
The Examiner relies on the following prior art references to show
unpatentability:
Mattos US 5,543,733 Aug. 6, 1996
Nguyen US 6,496,044 B1 Dec. 17, 2002

Claims 1, 2, 8, 9, 11, and 14-16 stand rejected under 35 U.S.C. §
102(b) as being anticipated by Mattos.
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Claims 1, 2, 8-12, and 14-17 stand rejected under 35 U.S.C. § 102(b)
as being anticipated by Nguyen.

ISSUES
The pivotal issues before us are whether:
i) the operation of the pull-down circuit 50 of Mattos corresponds
to the claimed current block circuit due to the opening of the transistor MNF
in the N-well bias circuit 30 current path from PAD 12 to the Vss terminal
18, and
ii) the operation of the ground bounce current reduction circuit
GBCR of Nguyen corresponds to the claimed current block circuit due to the
on-off operation of the transistor N10 in the current path of the N-well bias
circuit (NWC).

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence:
1. Mattos discloses (Fig. 2, col. 3, ll. 27-46) an over-voltage
tolerant input circuit including a external terminal PAD 12, an N-well bias
circuit 30 coupled to the PAD 12, and a pull-down circuit 50 coupled to the
N-well bias circuit 30.
2. Mattos further discloses (Figs. 2 and 4) a current path from the
PAD 12, the N-well bias circuit 30, the pull-down circuit 50 and the Vss
ground terminal 18.
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3. Mattos also discloses (Fig. 4, col. 4, ll. 4-11) that control signal
PD controls the on-off operation of the transistor MNF in the pull-down
circuit 50.
4. Nguyen discloses (Fig. 4) an over-voltage tolerant input circuit
including an external terminal PAD and an N-well bias circuit NWC and
N11.
5. Nguyen also discloses (Fig. 4) a ground bounce current
reduction circuit GBCR coupled to and in the current path of the N-well bias
circuit NWC and N11.
6. Nguyen further discloses (Fig. 4, col. 9, l. 62-col. 10, l. 4) that
the on-off operation of the transistor N10 in the ground bounce current
reduction circuit is controlled by input signal ND.
7. Nguyen further discloses (col. 1, ll. 55-58) the desirability of
providing an output circuit that is compatible with external input signals
arriving at an I/O pad that are at a higher voltage than the operating voltage
of the output circuit.

PRINCIPLES OF LAW
Anticipation
“It is axiomatic that anticipation of a claim under § 102 can be found
only if the prior art reference discloses every element of the claim.” See In
re King, 801 F.2d 1324, 1326 (Fed. Cir. 1986); Lindemann Maschinenfabrik
GMBH v. Am. Hoist & Derrick Co., 730 F.2d 1452, 1457 (Fed. Cir. 1984).
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
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Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citing Minn. Mining & Mfg.
Co. v. Johnson & Johnson Orthopaedics, Inc., 976 F.2d 1559, 1565 (Fed.
Cir. 1992)). “Anticipation of a patent claim requires a finding that the claim
at issue ‘reads on’ a prior art reference.” Atlas Powder Co. v. IRECO Inc.,
190 F.3d 1342, 1346 (Fed. Cir. 1999) (“In other words, if granting patent
protection on the disputed claim would allow the patentee to exclude the
public from practicing the prior art, then that claim is anticipated, regardless
of whether it also covers subject matter not in the prior art.”).

ANALYSIS
I. The anticipation rejection based on Mattos

With respect to the Examiner’s anticipation rejection of independent
claims 1, 8, and 15 based on Mattos, Appellant’s arguments focus on the
contention that, in contrast to the claimed overvoltage protection circuit, the
overvoltage protection circuit of Mattos does not include a current block
circuit. According to Appellant (App. Br. 8-9; Reply Br. 1-3), the pull-down
circuit 50 of Mattos, relied upon by the Examiner, operates to pull node
PAD to ground or to a low voltage, but does not operate to block current as
claimed.
We do not find Appellant’s arguments persuasive. We find no error
in the Examiner’s finding (Ans. 3), and there are no arguments to the
contrary from Appellant, that the pull-down circuit 50 of Mattos has a
control signal PD coupled to a gate of transistor MNF which is in a current
path of the N-well bias circuit 30 and the PAD 12. (FF 2). With this is
mind, we agree with the Examiner that, when the control signal PD causes
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the transistor MNF to open, current flowing in the N-well bias circuit current
path from PAD 12 to the Vss ground terminal 18 will be blocked. (FF 3).
Further, to whatever extent Appellant is contending that the
Examiner’s position is in error since Mattos never refers to the pull-down
circuit 50 as a “current block circuit”, we would point out that anticipation
"is not an 'ipsissimis verbis' test." In re Bond, 910 F.2d 831, 832-33 (Fed.
Cir. 1990) (citing Akzo N.V. v. United States Int'l Trade Comm'n, 808 F.2d
1471, 1479 n.11 (Fed. Cir. 1986)). "An anticipatory reference . . . need not
duplicate word for word what is in the claims." Standard Havens Products.
v. Gencor Indus., 953 F.2d 1360, 1369 (Fed. Cir. 1991).
For all of the above reasons, we find that all of the claim limitations
are present in the disclosure of Mattos, and we sustain the Examiner’s 35
U.S.C. § 102(b) rejection of appealed independent claims 1, 8, and 15, as
well as dependent claims 2, 9, 11, 14, and 16 not separately argued by
Appellant.

II. The anticipation rejection based on Nguyen

We also sustain the Examiner’s anticipation rejection of claims 1, 2,
8-12, and 14-17 based on Nguyen. Appellant’s arguments (App. Br. 9-10:
Reply Br. 3) mirror those made with respect to the rejection based on
Mattos, i.e., the ground bounce current reduction circuit (GBCR) of Nguyen
is not a current block circuit that would correspond to that claimed.
As with the previously discussed Mattos reference, Appellant’s
arguments do not convince us of any error in the Examiner’s finding (Ans.
5-7) that the on-off operation of the transistor N10 of the GBCR of Nguyen
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will operate as a current block in the current path of the N-well bias circuit
(NWC). (FF 5-6). We also agree with the Examiner (Ans. 8-9) that,
Appellant’s arguments (App. Br. 10) to the contrary notwithstanding,
Nguyen’s disclosure (FF 7) is directed to solving problems associated with
overvoltage situations where external input signals arriving at an I/O pad are
at a higher voltage than the operating voltage of the output circuit.

CONCLUSION
Based on the findings of facts and analysis above, we conclude that
i) the operation of the pull-down circuit 50 of Mattos corresponds
to the claimed current block circuit due to the opening of the transistor MNF
in the N-well bias circuit 30 current path from PAD 12 to the Vss terminal
18, and
ii) the operation of the ground bounce current reduction circuit
GBCR of Nguyen corresponds to the claimed current block circuit due to the
on-off operation of the transistor N10 in the current path of the N-well bias
circuit (NWC).

DECISION
The Examiner’s decision rejecting claims 1, 2, 8-12, and 14-17 under
35 U.S.C. § 102(b) is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2007).

AFFIRMED

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Application 11/273,825

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CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE CA 95134-1709