Ex Parte White

Board of Patent Appeals and Interferences

Jan 24, 2012

10990185 (B.P.A.I. Jan. 24, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/990,185 11/16/2004 John M. White APPM/9451/DISPLAY/AKT/RKK 4941
44257 7590 01/25/2012
PATTERSON & SHERIDAN, LLP - - APPM/TX
3040 POST OAK BOULEVARD, SUITE 1500
HOUSTON, TX 77056
EXAMINER
GAMBETTA, KELLY M
ART UNIT PAPER NUMBER
1715
MAIL DATE DELIVERY MODE
01/25/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte JOHN M. WHITE
____________

Appeal 2010-003827
Application 10/990,185
Technology Center 1700
____________

Before CHUNG K. PAK, TERRY J. OWENS, and PETER F. KRATZ,
Administrative Patent Judges.

PAK, Administrative Patent Judge.

DECISION ON APPEAL

Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
refusal to allow claims 9, 11, 12, 14, 15, 17, 19 through 21, 39, 41 through
43, 45, 46, and 52 through 60, all of the pending claims in the above-
identified application.1 We have jurisdiction under 35 U.S.C. § 6.

1 See Appeal Brief (“App. Br.”) filed June 24, 2009, 5-6; Response to
Notification of Non-Compliant Appeal Brief filed August 12, 2009, 3-4; and
Examiner’s Answer (“Ans.”) filed October 20, 2009, 2.
Appeal 2010-003827
Application 10/990,185

2

STATEMENT OF THE CASE

The subject matter on appeal is directed to a method of forming a gate
dielectric layer for use in thin film transistors (Spec. 4-5, paras. 0007-0013).
Details of the appealed subject matter are recited in representative claim 9
reproduced from the Claims Appendix to the Appeal Brief, as shown below:
9. A method of forming a gate dielectric layer on a
substrate, comprising:
forming a semiconductor layer comprising silicon on a
transparent substrate;
preheating the transparent substrate to a first temperature;
transferring the transparent substrate into a chemical
vapor deposition plasma processing chamber;
moving the transparent substrate to a first plasma
processing region of the plasma processing chamber;
flowing an oxidizing gas mixture into the plasma
processing chamber and generating an inductively coupled high
density plasma in the first plasma processing region at a
substrate surface temperature of no more than about 550°C to
form an oxidized layer on the semiconductor layer;
moving the substrate to a second plasma processing
region of the plasma processing chamber;
forming a dielectric layer on the oxidized layer to form a
gate dielectric layer, wherein at least a portion of the dielectric
layer is formed while the transparent substrate is positioned at
the second plasma processing region of the plasma processing
chamber; and
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annealing the transparent substrate at a second
temperature after forming the dielectric layer.
As evidence of unpatentability of the claimed subject matter, the
Examiner relies on the following prior art references at pages 2 and 3 of the
Answer:
Ikeda US 5,508,540 Apr. 16, 1996
Sandhu US 5,599,396 Feb. 4, 1997
Kawakami US 6,399,520 B1 June 4, 2002
Derwent Abstract on DE 29815132 published on Jan. 28, 1999,
Hoffman et al. (2007) (hereinafter referred to as “Hoffman”).2
Appellant seeks review of the Examiner’s rejection of claims 9, 11,
12, 14, 15, 17, 19 through 21, 39, 41 through 43, 45, 46, and 52 through 60
under 35 U.S.C. § 103(a) as unpatentable over the combined disclosures of
Kawakami, Ikeda, Sandhu, and Hoffman.

RELEVANT FACTUAL FINDINGS, PRINCIPLES OF LAW, ISSUE,
ANALYSIS AND CONCLUSION
Appellant does not dispute the Examiner’s finding that Kawakami
discloses a method of forming a gate insulator (corresponding to the claimed
gate dielectric layer) on a substrate, comprising forming a semiconductor
layer comprising silicon on a substrate, inclusive of a known transparent
substrate, as evidenced by Hoffman, preheating the transparent substrate to a
first temperature, transferring or moving the substrate into a first plasma
processing chamber (32), flowing an oxidizing gas mixture into the first
plasma processing chamber at a temperature less than 550oC and generating

2 Appellant does not argue that the content of the Derwent Abstract is not
available as “prior art”. (See generally App. Br. and Reply Br.)
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a high density plasma containing oxygen with a microwave power supply to
oxidize and form a silicon oxynitride insulating layer3 (a first dielectric
layer), transferring or moving the resulting substrate to a second plasma
processing chamber (33), and forming a silicon nitride insulating layer (a
second dielectric layer corresponding to the claimed dielectric layer) on the
silicon oxynitride layer via chemical vapor deposition (CVD). (Compare
Ans. 4-5 with App. Br. 15-22 and Reply Br. 2-3.) Nor does Appellant
dispute the Examiner’s determination that it would have been obvious to
anneal the silicon nitride insulation layer (dielectric layer) deposited
substrate from the method taught by Kawakami at a second temperature,
with a reasonable expectation of successfully reducing the number of
dangling bonds in the layer. (Compare Ans. 5 with App. Br. 15-22 and
Reply Br. 2-3.) Rather, Appellant contends that Kawakami does not teach or
suggest employing a single chemical vapor deposition processing chamber
having first and second plasma processing regions to form its oxidized and
dielectric layers. (See App. Br. 15-22 and Reply Br. 2-3.) Appellant also
contends that one of ordinary skill in the art would not have been led to
employ the inductively coupled high density plasma taught by Sandhu to
produce the silicon oxynitride or silicon oxide dielectric layer in the method
suggested by Kawakami and Ikeda. (See Id.)

3 Appellant does not argue that the silicon oxynitride insulating layer taught
by Kawakami is not an oxidized layer. (See App. Br. 15-22.) Moreover,
Appellants acknowledge at page 16 of the Appeal Brief that Kawakami
teaches silicon oxide or silicon oxynitride layer can be deposited as a gate
insulating (dielectric) layer and that Ikeda teaches a silicon oxide layer as a
known gate insulating (dielectric) layer.
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Thus, the dispositive question raised by the Examiner and Appellants
is: Has the Examiner reversibly erred in determining that one of ordinary
skill in the art, armed with the knowledge of Kawakami, Ikeda, Hoffman,
and Sandhu would have been led to employ the inductively coupled high
density plasma taught by Sandhu in the first plasma processing region of a
chemical vapor deposition processing chamber to form its gate silicon
oxynitride or silicon oxide insulating (first dielectric) layer corresponding to
the claimed oxidized layer and then form its gate silicon nitride insulating
(second dielectric) layer corresponding to the claimed dielectric layer in the
second plasma processing region of the chemical vapor deposition
processing chamber within the meaning of 35 U.S.C. § 103(a)? On this
record, we answer this question in the negative.
As correctly found by the Examiner at pages 4 and 5 of the Answer,
Kawakami impliedly or expressly discloses using either a cluster having first
and second plasma processing chambers or a single chamber having first and
second plasma processing regions, to form its gate silicon oxynitride
insulating (first dielectric) layer corresponding to the claimed oxidized layer
and gate silicon nitride insulating (second dielectric) layer corresponding to
the claimed dielectric layer. (Compare Ans. 3-4 with App. Br. 19) In
particular, Kawakami teaches using a plasma processing unit (32) for
generating a microwave “high density plasma” for depositing a gate
insulating silicon oxynitride layer (an oxidized dielectric layer) and a
chemical vapor deposition (CVD) processing unit (33) for depositing a
second gate insulating silicon nitride layer (claimed dielectric layer). (See
col. 6, ll. 3-19.) Kawakami also teaches that “both of these units for plasma
processing 32 and CVD processing 33 can be replaced by a single chamber
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unit for plasma enhanced CVD processing.” (See id.at ll. 24-26) Implicit in
this teaching of Kawakami is that the single chamber having two different
plasma generating regions can be used to replace two plasma chambers for
doing the same since a different dielectric layer is produced from a different
location and two plasma generating chambers connote two different regions
or locations.4 KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007)
(“[A]nalysis [of whether the subject matter of a claim would have been
obvious under § 103] need not seek out precise teachings directed to the
specific subject matter of the challenged claim, for a court can take account
of the inferences and creative steps that a person of ordinary skill in the art
would employ.”); In re Preda, 401 F. 2d 825, 826 (CCPA 1968) (In
determining what a reference discloses, “it is proper to take into account not
only specific teachings of the reference but also the inferences which one
skilled in the art would reasonably be expected to draw therefrom.”)
Although Kawakami does not mention using an inductively coupled
high density plasma to form its first (silicon oxynitride) dielectric layer,
Sandhu teaches, at column 1, lines 10-18 and 32-48 and column 2, lines 5-
25, that its high density chemical vapor deposition plasma can be used to
deposit a layer, including a dielectric film, onto a workpiece (substrate) or
fill high aspect ratio spaces and can be formed by an inductive coil placed on

4 Note also that for a single chamber to replace two different chambers to
produce two different plasmas as required by Kawakami, the single chamber
must have either one plasma processing region for producing two different
plasmas or two plasma processing regions for producing two different
plasmas. In other words, one of ordinary skill in the art would have readily
envisaged the single chamber having two plasma processing regions from
the teachings of Kawakami due to the limited options for producing two
different plasmas in a single chamber.
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the outside of a chemical vapor deposition chamber via inductively ionizing
the deposition gases (plasmas). Sandhu, like Kawakami, teaches using a
high density plasma to deposit a dielectric layer. Id.
Given the above teachings, we concur with the Examiner that one of
ordinary skill in the art, armed with the knowledge of Kawakami, Ikeda,
Hoffman, and Sandhu would have been led to employ an inductive coil or
microwave generating means on the first plasma processing region of the
chemical vapor deposition chamber to generate a high density plasma
(inductively coupled high density plasma) to deposit a silicon oxynitride
insulating (first dielectric) layer prior to depositing the silicon nitride
insulating (second dielectric) layer via generating a regular high density
chemical vapor deposition plasma from the second plasma processing region
of the same chemical vapor deposition chamber. In other words, the use of
one known high density plasma generating means for depositing a dielectric
layer, in lieu of another high density plasma generating means for doing the
same, would have been obvious to one of ordinary skill in the art. KSR, 550
U.S. at 417 (quoting Sakraida v. Ag Pro, Inc., 425 U.S. 273, 282
(1976)(“[W]hen a patent ‘simply arranges old elements with each
performing the same function it had been known to perform’ and yields no
more than one would expect from such an arrangement, the combination is
obvious.”); In re Mayne, 104 F.3d 1339, 1340 (Fed. Cir. 1997) (noting that
the substitution of one known element for a known equivalent is prima facie
obvious).
Appellant appears to contend that Kawakami’s statement regarding
the use of a single chamber is not sufficiently enabling. (See App. Br. 19.)
However, Appellant has not demonstrated that the disclosure of Kawakami,
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coupled with information known in the art, would not enable one of ordinary
skill in the art to make and use of a single chamber having two plasma
processing regions. In particular, Appellant has not shown that one of
ordinary skill in the art would not have been able to make or use a single
chamber comprising one region having an inductive coil for producing an
inductively coupled high density plasma and another region without an
inductive coil for producing a regular high density plasma in a chemical
vapor deposition chamber, without undue experimentation, based on the
information provided by Kawakami, together with the information known in
the art, including that taught by Sandhu.. Compare In re Spence, 261 F.2d
244, 246 (CCPA 1958). Appellant has not even discussed why factors, such
as (1) the quantity of experimentation necessary, (2) the amount of direction
or guidance presented, (3) the presence or absence of working examples, (4)
the nature of the invention, (5) the state of the prior art, (6) the relative skill
of those in the art, (7) the predictability or unpredictability of the art, and (8)
the breadth of the claims, would supports his or her position that
Kawakami’s disclosure relating to the use of a single chamber to replace two
chambers for producing two different plasmas is not enabling. See In re
Vaeck, 947 F.2d 488 (Fed. Cir. 1991).
Thus, on this record, we determine that the Examiner has not
reversibly erred in determining that one of ordinary skill in the art, armed
with the knowledge of Kawakami, Ikeda, Hoffman, and Sandhu, would have
been led to employ the inductively coupled high density plasma taught by
Sandhu in the first plasma processing region of a chemical vapor deposition
processing chamber to form Kawakami’s gate silicon oxynitride or silicon
oxide insulating (first dielectric) layer corresponding to the claimed oxidized
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layer and then form Kawakami’s gate silicon nitride insulating (second
dielectric) layer corresponding to the claimed dielectric layer in the second
plasma processing region of the chemical vapor deposition processing
chamber within the meaning of 35 U.S.C. § 103(a). It follows that based on
the fact findings and reasons set forth in the Answer, we affirm the
Examiner’s § 103(a) rejection.

ORDER
In view of the foregoing, it is
ORDERED that the decision of the Examiner rejecting the claims on
appeal under 35 U.S.C. § 103(a) is AFFIRMED; and
FURTHER ORDERED that no time period for taking any subsequent
action in connection with this appeal may be extended under 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED

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