Ex Parte Whitaker

Board of Patent Appeals and Interferences

May 20, 2011

10432309 (B.P.A.I. May. 20, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/432,309 10/29/2003 Martin Whitaker ASP 0002 PA 7315
23368 7590 05/20/2011
DINSMORE & SHOHL LLP
FIFTH THIRD CENTER, ONE SOUTH MAIN STREET
SUITE 1300
DAYTON, OH 45402-2023
EXAMINER
ZAMAN, FAISAL M
ART UNIT PAPER NUMBER
2111
MAIL DATE DELIVERY MODE
05/20/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte MARTIN WHITAKER
____________________

Appeal 2009-007809
Application 10/432,3091
Technology Center 2100
____________________

Before JAY P. LUCAS, THU A. DANG and CAROLYN D. THOMAS,
Administrative Patent Judges.

LUCAS, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals from a final rejection of claims 1 to 12 under
authority of 35 U.S.C. § 134(a). The Board of Patent Appeals and
Interferences (BPAI) has jurisdiction under 35 U.S.C. § 6(b).

We affirm the rejections.

1 Application filed October 29, 2003. Appellant claims the benefit under
35 U.S.C. § 119 the PCT of various applications dating to November 21,
2000. The real party in interest is Aspex Technology, Ltd.
Appeal 2009-007809
Application 10/432,309
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Appellant’s invention relates to a modification to the Peripheral
Component Interconnect (PCI) databus standard to allow broadcasting data
to multiple targets on the bus. In the words of Appellant:
With the advent of modem electronic
components running at much higher speeds than
when the original specifications for many
databuses were drawn up, and the development of
many more types of components able to connect to
these databuses, the efficient use of the limited
transmission bandwidth along databuses is
essential in achieving good overall system
performance in computerised systems.
Examples of high-performance plug-in
components which are compatible with the
PCI databus standard include video capture cards,
Double Data Rate (DDR) memory technologies,
IEEE 1394 communication cards, cable and
xDSLmodems and LAN cards based on optical or
Fast Ethernet protocols. Equally compatible are
surface mounted components present on
motherboards and daughterboards of computer
systems. Many of these types of PCI databus
compatible components require heavy bandwidth
usage.
A common limiting factor for overall system
performance of computerised systems are
bottlenecks caused when databus bandwidth is not
enough to accommodate all the data that needs
transporting simultaneously. For example, when
large amounts of information are frequently
transferred to and from memory, the memory
databus bandwidth can quickly become saturated
leading to a cap on performance. This problem is
exacerbated in high performance computer
systems, particularly within systems that contain
more than one processing unit wherein a
transaction initiator may be transmitting data to
one or more responding targets simultaneously.
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In these situations data broadcasting (i.e. the
simultaneous transfer of data from a single source
location to multiple destinations) is often required.
If the system databuses used in these high-
performance systems do not support broadcast
transfers then the data has to be individually and
sequentially transferred to each of the required
responding targets, unnecessarily consuming bus
bandwidth and increasing both the time taken and
the number of processor cycles needed to complete
the task. These are detrimental factors to the
performance of the system and need to be
minimised.
. . . .
The only other way in which the PCI
databus specification allows more than one
component to listen in on data not being directly
transmitted to that component is via ‘VGA palette
snooping’. This is a means of having a passive
listener on the PCI bus listen in, or ‘snoop’, on the
data being transmitted across the PCI bus and is
used when special VGA video display cards and
other high-end display-related components, such as
MPEG decoder cards, need to be able to look at
the video card’s VGA palette to determine what
colours are currently in use. This feature is only
rarely used and is also unsuitable for transmitting
large blocks of data to multiple components at
speed as only a restrictive address range (only of
interest to display-related components) is passed
along. Again, no handshaking is present in “VGA
palette snooping” and a further drawback is
present in that an assumption is made that the
passive listener is always at least as fast as the
intended responding target in being able to receive
the transmitted data, otherwise the passive listener
may miss some information.
. . . .
It is with a view to solving these problems
that there is provided a method of broadcasting
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data to multiple targets across a system bus, such
as the peripheral component interconnect (PCI)
bus, that does not normally support broadcast
transfers, in which one target responds to the bus
transaction and the remaining targets listen in on
the bus transaction to receive data from the system
bus, the method comprising the responding target
stalling the bus transaction when any of the
listening targets communicate to the responding
target that they are temporarily unable to accept
the data on the bus.
(Spec. 1, l. 17 to 2, l. 17; Spec. 3, ll. 5 to 18; Spec. 5, ll. 9 to 16)
The following illustrates the claims on appeal:
Claim 1:
1. A method of broadcasting data to multiple
targets across a system bus that does not normally
support broadcast transfers, in which one target
responds to a bus transaction and remaining targets
listen in on the bus transaction to receive data from
the system bus, the method comprising the
responding target stalling the bus transaction when
any of the listening targets communicate to the
responding target that they are temporarily unable
to accept the data on the bus.

The prior art relied upon by the Examiner in rejecting the
claims on appeal is:
MacWilliams US 5,572, 703 Nov. 05, 1996
Jaramillo US 6,397,279 B1 May 28, 2002
Microsoft Computer Dictionary 141, 512 (Microsoft Corp. 5th ed.
2002).
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Application 10/432,309
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REJECTIONS
The Examiner rejects the claims as follows:

R1: Claims 1 to 3 and 5 to 12 stand rejected under 35 U.S.C. § 102(e) for
being anticipated by Jaramillo.
R2: Claim 4 stands rejected under 35 U.S.C. § 103(a) for being obvious
over Jaramillo in view of MacWilliams.

We will review the rejections in the order argued. We have only
considered those arguments that Appellant actually raised in the Briefs.
Arguments Appellant could have made but chose not to make in the Briefs
have not been considered and are deemed to be waived. See
37 C.F.R. § 41.37(c)(1)(vii).

ISSUE
The issue is whether Appellant has shown that the Examiner erred in
rejecting the claims under 35 U.S.C. § 102(e) and 35 U.S.C. § 103(a). The
issue specifically turns on whether Jaramillo teaches the elements of the
claims as required for anticipation.

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.
1. Appellant has invented a method for using inherent features of the PCI
databus specification, such as “snooping”, to permit broadcasting data to
multiple target cards on the PCI bus. (Spec. 3, ll. 5 to 19). The method
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requires slowing or stalling the transmission of data to allow slower
boards to keep pace with the transmission. (Spec. 5, ll. 18 to 27).

PRINCIPLES OF LAW

Appellants have the burden on appeal to the Board to demonstrate
error in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86
(Fed. Cir. 2006) (“On appeal to the Board, an applicant can overcome a
rejection [under § 103] by showing insufficient evidence of prima facie
obviousness or by rebutting the prima facie case with evidence of secondary
indicia of nonobviousness.”) (quoting In re Rouffet, 149 F.3d 1350, 1355
(Fed. Cir. 1998)).
“It is common sense that familiar items may have obvious uses
beyond their primary purposes, and a person of ordinary skill often will be
able to fit the teachings of multiple patents together like pieces of a puzzle.”
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 402 (2007).
“It is axiomatic that anticipation of a claim under § 102 can be found
only if the prior art reference discloses every element of the claim . . . .” In
re King, 801 F.2d 1324, 1326 (Fed. Cir. 1986): see also Lindemann
Maschinenfabrik GMBH v. American Hoist & Derrick Co., 730 F.2d 1452,
1458 (Fed. Cir. 1984).
Our reviewing court states in In re Zletz, 893 F.2d 319, 321 (Fed. Cir.
1989) that “claims must be interpreted as broadly as their terms reasonably
allow.” “[T]he words of a claim ‘are generally given their ordinary and
customary meaning.’” Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed.
Cir. 2005) (en banc) (internal citations omitted). “[T]he ordinary and
customary meaning of a claim term is the meaning that the term would have
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to a person of ordinary skill in the art in question at the time of the invention,
i.e., as of the effective filing date of the patent application.” Id. at 1313.
ANALYSIS

Arguments with respect to the rejection
of claims 1 to 3 and 5 to 12
under 35 U.S.C. § 102(e) [R1]

The Examiner has rejected the noted claims for being anticipated by
Jaramillo. Appellant has presented a number of arguments against the
rejection, which we will consider seriatim.
Arguments concerning Claim 1 are first presented. Considering
Figure 5 of the Jaramillo reference, the Appellant first challenges the
Examiner’s calling PCI Arbiter 401 a target. (App. Br. 6, bottom). “This is
clearly a wrong interpretation of the term ‘target’ which has a plain and clear
meaning to the skilled addressee as an ultimate recipient of information/data
from the bus . . . .” (Id.). The Examiner interprets the term “target” as used
in the claim to fairly read on the PCI Arbiter as the intended recipient of the
initial bus request described in Jaramillo, column 5, lines 53 to 57. (Ans. 8,
top). We find that even according to the definition of the Appellant, the
general term “target” is broadly but fairly read on the recipient of the signals
as interpreted by the Examiner, for the purposes of anticipation. (See In re
Zletz, cited above.) The bus request mask is targeted to the PCI arbiter,
which receives that signal. Even in Jaramillo, the reference of record, the
term “target” is used in a broader context than the Appellant would suggest,
as Zaramillo uses the term for the PCI Target Agent. As the Examiner
mentioned, there is no specific definition of target in the Specification.
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(Ans. 8, top; see In re Phillips, cited above.) As such, we do not find the
Examiner’s interpretation to be in error on this point.
Appellant further argues that “it is clear that the term ‘bus transaction’
refers to the transmission of the ‘main’ data to any one or more of the
responding or snooping targets.” (App. Br. 7, top). The Examiner, in
response, finds that the transactions disclosed in Jaramillo occur on the main
system bus, namely a PCI Initiator Agent 402-404 requesting access to the
PCI Target Agent 405 and the subsequent response from the PCI Arbiter
401. (Ans. 8, middle). The Examiner rightly points out that claim 1 does
not discuss a “main data”. (Id.). Anticipation only requires that the claimed
elements are presented in a single reference. (See In re King, cited above.)
We find that the reference does teach the cited elements as indicated by the
column and line discussion of the Examiner.
Next the Appellant argues: “Clearly, the PCI target agent 405 is not
listening in on the data transfer itself, but, in fact, determines which PCI
initiator agent 402, 403 and 404 is trying to access it.” (App. Br. 8, top).
The Examiner points to Jaramillo, column 6, line 63, which contains that
exact teaching. (Ans. 9, middle). We do not find this finding by the
Examiner to be in error.
Finally, the Appellant argues that in Jaramillo, the bus denial signal
denies access to the PCI initiator subsequent access to the PCI bus, and not
as claimed. (App. Br. 8, bottom). First, we find the claim does not discuss
time sequencing as argued. However, the Examiner counters with column
and line in Jaramillo showing immediate response to the bus denial signal,
rendering Appellant’s argument unconvincing. (Ans. 10, top). We also do
not find the Examiner’s finding to be in error on this point.
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With regard to Appellant’s arguments concerning claims 5, 6, 11 and
12, we endorse and adopt the Examiner’s responses. (Ans. 10, 11).

Arguments with respect to the rejection
of claim 4
under 35 U.S.C. § 103(a) [R2]

The Examiner has rejected the noted claims for being obvious over
Jaramillo and MacWilliams, the latter reference adding the teaching of
specifically entering the signals from the targets into an OR gate. We do not
find error with this rejection as stated by the Examiner.
CONCLUSIONS OF LAW
Based on the findings of facts and analysis above, we conclude that
Appellant has not shown that the Examiner erred in rejecting claims 1 to 12.

DECISION
We affirm the Examiner’s rejections R1 and R2 of claims 1 to 12.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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