Ex Parte Welland et al

Patent Trial and Appeal Board

May 17, 2016

12650545 (P.T.A.B. May. 17, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/650,545 12/31/2009
60939 7590 05/19/2016
MAXIMILLIAN R. PETERSON
PO Box 88112 Rabbit Hill PO
Edmonton, AB T6R OMS
CANADA
FIRST NAMED INVENTOR
David R. Welland
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
SILA288Cl 7431
EXAMINER
LE, DINH THANH
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
05/19/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
USPTOI@PETERSONIPLA W.COM
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DAVID R. WELLAND, DONALD A. KERTH,
and CAIYI WANG
Appeal2014-008952
Application 12/650,545
Technology Center 2800
Before TERRY J. OWENS, ELIZABETH M. ROESEL, and
JEFFREY R. SNAY Administrative Patent Judges.
OWENS, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
The Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 61-80. We have jurisdiction under 35 U.S.C. § 6(b).
The Invention
The Appellants claim an integrated circuit and a method for reducing
interference caused by signals present at an interface pin of the integrated
circuit. Claim 61 is illustrative:
61. An integrated circuit (IC) comprising a filter, the filter
compnsmg:
an [sic] resistive-capacitive filter coupled to a first
interface pin of the integrated circuit (IC), the resistive-
capacitive filter comprising a capacitor coupled between the
Appeal2014-008952
Application 12/650,545
first interface pin and a second interface pin of the integrated
circuit (IC), and a resistor coupled to the first interface
pm,
wherein the resistive-capacitive filter isolates the first
interface pin while allowing a signal received from an external
oscillator to pass through to circuitry within the integrated
circuit (IC),
wherein the filter is adapted to reduce interference in the
integrated circuit (IC).
Fay
Weber
Muth
Walsh
The References
us 4,703,390
us 5,929,698
US 6,628,490 B2
US 6,772,361 B2
The Rejections
Oct. 27, 1987
July 27, 1999
Sep.30,2003
Aug. 3, 2004
The claims stand rejected as follows: claims 61, 65---68 and 72-75
under 35 U.S.C. § 102(b) over Weber, claims 61 and 63-80 under
35 U.S.C. § 102(e) over \Valsh and under 35 U.S.C. § 103 over \Valsh in
view of Fay, and claim 62 under 35 U.S.C. § 103 over Weber in view of
Muth and over Walsh in view of Fay and Muth. 1
OPINION
We reverse the rejection under 35 U.S.C. § 102(b) over Weber as to
claims 61 and 72-75 and affirm it as to claims 65---68, reverse the rejection
of claim 62 under 35 U.S.C. § 103 over Weber in view of Muth, affirm the
rejections of claims 61and63-80 under 35 U.S.C. §102(e) over Walsh and
1 A rejection of claims 61-71, 65, 74, 79 and 80 under 35 U.S.C. § 112,
second paragraph is withdrawn in the Examiner's Answer (Ans. 3).
2
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Application 12/650,545
under 35 U.S.C. § 103 over Walsh in view of Fay, and affirm the rejection
under 35 U.S.C. § 103 of claim 62 over Walsh in view of Fay and Muth.
Rejection of claims 61 and 72-75 under
35 U.S.C. § 102(b) over Weber
An examiner has the initial burden of establishing a prima facie case
of anticipation by pointing out where all of the claim limitations appear,
either expressly or inherently, in a single reference. See In re Spada, 911
F.2d 705, 708 (Fed. Cir. 1990); Corning Glass Works v. Sumitomo Elec.
U.S.A., Inc., 868 F.2d 1251, 1255-56 (Fed. Cir. 1989); In re King, 801 F.2d
1324, 1327 (Fed. Cir. 1986).
We need address only the independent claims ( 61 and 72). Those
claims require an oscillator that is external to an integrated circuit.
Weber discloses a filter circuit comprising a sub-filter (A) including
first (2,3) and second ( 4,5) low-pass filters and, within an integrated circuit,
l) a sub-filter (B) including tv,ro ( 6, 7 and 8,9) filter circuits and an
amplifier (10), and 2) a signal processing circuit (C) (col. 2, 11. 4--25, 37--42;
Fig. 1).
The Examiner relies upon Weber's sub-filter A or signal processing
circuit C as corresponding to the Appellants' external oscillator (Ans. 4).
The Examiner has not established that Weber's sub-filter A is an
oscillator or that signal processing circuit C is external to the integrated
circuit (col. 2, 11. 5---6; Fig. 1 ).
Thus, the Examiner has not pointed out where each limitation of the
Appellants' claims appears in a single reference. Accordingly, we reverse
the rejection of claims 61 and 72-75 under 35 U.S.C. § 102(b) over Weber.
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Application 12/650,545
Rejection of claim 62 under 35 U.S. C. § 103
over Weber in view of Muth
The Examiner does not rely upon any obviousness rationale or
disclosure in Muth that remedies the deficiency in Weber as to claim 61
from which claim 62 depends (Final Act. 10-11 ). Hence, we reverse the
rejection of claim 62 under 35 U.S.C. § 103 over Weber in view of Muth.
Rejection of claims 65-68 under 35 U.S.C. § 102(b) over Weber
The Appellants argue claims 65---68 as a group (App. Br. 12-13). We
therefore limit our discussion to one claim, i.e., claim 65, which is the sole
independent claim among claims 65---68. Claims 66-68 stand or fall with
claim 65. See 37 C.F.R. § 41.37(c)(l)(iv) (2012).
The Appellants assert that the Examiner has failed to show "how
Weber teaches 'sending or receiving signals that alternate between a high
and a low state to convey information,' or 'a filter formed on the integrated
circuit for reducing interference caused by signals at the interface pin of the
integrated circuit,' or 'wherein the filter isolates an impedance change from
circuitry within the integrated circuit while allowing the sending or receiving
of signals."' (App. Br. 12-13).
Weber's integrated circuit includes an interface pin (13) and
filters (6,7 and 8,9) which, by filtering out high-frequency signals, reduce
interference caused by those signals at the interface pin (13) (col. 2, 11. 4--42;
Fig. 1). The filters (6,7 and 8,9) are coupled between the interface pin (13)
and other circuitry (amplifier 10, signal processing circuit C) on the
integrated circuit and isolate an impedance change from the circuitry while
allowing low frequency signals to be sent to the circuitry (see id.). The
Appellants provide no substantive argument to the contrary. See In re Lovin,
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Application 12/650,545
652 F.3d 1349, 1357 (Fed. Cir. 2011) (Rule 41.37 "require[s] more
substantive arguments in an appeal brief than a mere recitation of the claim
elements and a naked assertion that the corresponding elements were not
found in the prior art").
Hence, we affirm the rejection of claims 65---68 under
35 U.S.C. § 102(b) over Weber.
Rejections of claims 61 and 63--80 under 35 U.S.C. §102(e) over
Walsh and under 35 U.S. C. § 103 over Walsh in view of Fay,
and claim 62 under 35 U.S. C. § 103 over Walsh
in view of Fay and Muth
The Appellants argue only independent claims 61 and 65, and with
respect to independent claim 72 incorporate their arguments regarding
claim 61 (App. Br. 14--19; Reply Br. 4---6). Consequently, we limit our
discussion to claims 61 and 65. Claim 61 's dependent claims and claim 72
and its dependent claims stand or fall with claim 61, and claim 65' s
dependent claims stand or fall with claim 65. See 37 C.F.R.
§ 41.37(c)(l)(iv) (2012).
Claim 61
Walsh discloses a real time clock (R TC) which preferably is formed
as a single integrated circuit and comprises accuracy detection logic (80)
which receives a clock signal and determines the accuracy of its frequency
(col. 12, 11. 28-30; col. 16, 11. 32-35). The accuracy detection logic (80) has
circuitry including 1) a resistor-capacitor (RC) network (90) which receives
a clock signal produced by an oscillator (64) and filters that signal to
produce an output voltage (Vo), 2) a comparator (92) which receives the
output voltage (Vo) and asserts an output signal (VL) when the clock signal
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Application 12/650,545
is below a lower limit of an acceptable frequency range, and 3) a
set-rest (SR) flip-flop (94) which latches the asserted output signal (VL) to
produce an error signal received by an access unit ( 66) until that unit asserts
a reset signal (col. 18, 11. 1-17; Figs. 5B, 6).
The Appellants argue that Walsh's oscillator (64) and accuracy
detection logic (80) are on the same integrated circuit and that, therefore, the
oscillator (64) is not external to the integrated circuit (App. Br.15; Reply
Br. 4--5).
Walsh discloses that a single integrated circuit RTC is merely a
preferred embodiment (col. 12, 11. 28-30). References are not limited to
their preferred embodiments. See In re Kohler, 475 F.2d 651, 653 (CCPA
1973); In re Mills, 470 F.2d 649, 651 (CCPA 1972); In re Bozek, 416 F.2d
1385, 1390 (CCPA 1969). Hence, Walsh indicates that the portions of the
RTC (Fig. 5B) can be separate integrated circuits such that the oscillator (64)
is external to the accuracy detection logic (80)' s integrated circuit.
The Appellants assert that Walsh's accuracy detection logic (80)'s
filter (90) does not reduce interference in the integrated circuit (Reply Br. 5).
That filter removes undesired frequencies (col. 18, 11. 3---6) and,
consequently, reduces interference from those frequencies in the detection
logic (80)' s integrated circuit.
Thus, we are not persuaded of reversible error in the rejection of
independent claims 61 and 72 and their dependent claims.
Claim 65
The Appellants assert that Walsh's filter (90) is not coupled between
an interference pin of an integrated circuit and other circuitry on the
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integrated circuit and does not isolate an impedance change from circuitry
within the integrated circuit while allowing the sending or receiving of
signals (Reply Br. 6).
Walsh's filter (90) is coupled to an interface pin between the accuracy
detection logic (80)'s integrated circuit and the oscillator (64) and, by
removing undesired frequencies, isolates an impedance change from
circuitry (comparator 92 and flip-flop 94) within the integrated circuit while
allowing signals having desired frequencies to be sent to the access unit ( 66)
(col. 18, 11. 1-17; Figs. 5B, 6).
Therefore, we are not convinced of reversible error in the rejection of
claim 65 and its dependent claims.
DECISION/ORDER
The rejection under 35 U.S.C. § 102(b) over Weber is reversed as to
claims 61 and 72-75 and affirmed as to claims 65---68. The rejection of
claim 62 under 35 U.S.C. § 103 over Weber in view of Muth is reversed.
The rejections of claims 61and63-80 under 35 U.S.C. §102(e) over Walsh
and under 35 U.S.C. § 103(a) of over Walsh in view of Fay, and the
rejection under 35 U.S.C. § 103(a) of claim 62 over Walsh in view of Fay
and Muth are affirmed.
It is ordered that the Examiner's decision is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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