Ex Parte Welchko et al

Patent Trial and Appeal Board

Sep 28, 2016

12704614 (P.T.A.B. Sep. 28, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
121704,614 02/12/2010
70422 7590 09/30/2016
LKGlobal (GM)
7010 E. COCHISE ROAD
SCOTTSDALE, AZ 85253
FIRST NAMED INVENTOR
BRIAN A. WELCHKO
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO.
P010431-ATC-CD
(003.0741)
CONFIRMATION NO.
6523
EXAMINER
ALSOMIRI, MAID! A
ART UNIT PAPER NUMBER
3667
NOTIFICATION DATE DELIVERY MODE
09/30/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docketing@lkglobal.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BRIAN A. WELCHKO, SILVA HITI, ABBAS RAFT ARI,
JEONG J. PARK, HANNE BUUR, WEI D. WANG, BRIAN R. MEDEMA,
WILLIAM R. CAWTHORNE, and JACKIE L. CUI
Appeal2014-002803
Application 12/704,6141
Technology Center 3600
Before STEFAN STAICOVICI, KEN B. BARRETT, and
FREDERICK C. LANEY, Administrative Patent Judges.
LANEY, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Brian A. Welchko et al. (Appellants) appeal under 35 U.S.C. § 134(a)
from the Examiner's final decision rejecting claims 1-19 and 21 under
35 U.S.C. § 102(b) as anticipated by Weiberle (US 2008/0052494 Al,
published Feb. 28, 2008). We have jurisdiction over this appeal under 35
U.S.C. § 6(b).
SUMMARY OF DECISION
We AFFIRM-IN-PART.
According to Appellants, the real party in interest is GM Global
Technology Operations, Incorporated. Appeal Br. 1 (filed March 28, 2013).
Appeal2014-002803
Application 12/704,614
INVENTION
Appellants' invention relates "to a method and system for controlling
electrical systems of vehicles." Spec. i-f 1.
Claims 1, 10, and 14 are independent. Claims 1 and 10 are illustrative
of the claimed inventions and read as follows:
1. A method for controlling an electrical system of a vehicle
using first data for a first path of calculations and second data
for a second path of calculations, the first path comprising a
first plurality of calculations of generating a value of a
parameter pertaining to the electrical system, the second path
comprising a second plurality of calculations of monitoring the
electrical system with respect to the first path, and the method
comprising the steps of:
determining whether the first data is ready for processing
along the first path using a processor;
performing calculations of the first path using the first
data and the processor; and
performing calculations of the second path using the
processor and the second data if the first data is not ready for
processing along the first path.
10. A method for controlling an electrical system of a vehicle
using control data for a control path of a first plurality of
calculations of the electrical system and monitoring data for a
monitoring path of a second plurality of calculations for
monitoring the control path, the method comprising the steps
of:
determining whether a plurality of data frozen flags are
active using a processor, each of the plurality of data frozen
flags corresponding to a respective one of the first plurality of
calculations of the first path and a respective one of the second
plurality of calculations of the second path;
performing those of the first plurality of calculations for
which the corresponding data frozen flag is inactive using the
processor;
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Application 12/704,614
performing those of the second plurality of calculations
for which the corresponding data frozen flag is active using the
processor;
storing results of the second plurality of calculations
upon completion of the second plurality of calculations; and
setting the data frozen flag to inactive using the processor
upon completion of the second plurality of calculations.
ANALYSIS
Claims 1-5
Appellants assert the Examiner's rejection of claim 1 is improper
because "[ d]ifferent steps of Weiberle ... are performed by different
processors in Weiberle." Appeal Br. 5. In the Final Office Action, the
Examiner finds "W eiberle teaches performing different steps with the same
processor," however. Final Act. 7 (citing Weiberle i-fi-18, 12-14), Ans. 2
(same). Appellants argue that the Examiner's finding is incorrect because
Weiberle specifies that "two execution units" are utilized. Appeal Br. 5.
For the following reasons, Appellants' argument is not persuasive.
Claim 1 refers to "a processor," without any limitations to the number
of "execution units" that may be present on the processor. Under the
broadest reasonable interpretation, and in light of Appellants' Specification,
we agree with the Examiner that there is nothing inherently limiting about
the term "processor" that excludes multiple "execution units" within the
processor. Appellants do not identify anything within claim 1, or the
Specification, indicating the term "processor" is limited to a single execution
unit. Appellants point out that claim 1 refers to "a processor" and
subsequently "the processor" (id.), but Appellants do not direct us to
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Application 12/704,614
anything showing a skilled artisan, when construing the term "processor,"
would have limited it to a single execution unit.
Contrarily, Weiberle evidences skilled artisans construe the term
"processor" to broadly include processing devices with multiple execution
units: "[t]he present invention is based on a method and a device for operand
processing in a processor unit having at least two execution units .... "
Weiberle i-fi-f l, 8. "Prior art references may be 'indicative of what all those
skilled in the art generally believe a certain term means ... [and] can often
help to demonstrate how a disputed term is used by those skilled in the art.'"
In re Cortright, 165 F.3d 1353, 1358 (Fed. Cir. 1999). Appellants' narrow
interpretation of claim 1 is unpersuasive and thus, we decline to adopt it.
Because Appellants fail to raise properly any other patentability
arguments for claim 1, we sustain the Examiner's rejection. Appellants
similarly assert claims 2-5, which depend from claim 1, are patentable
because "W eiberle does not disclose [the steps of claims 2-5] being
performed by a single processor, as is inherently recited in Appellant[ s ']
[claims 2-5] via the phrase 'the processor."' Appeal Br. 7-8. Notably,
Appellants fail to raise properly any other patentability arguments for claims
2-5. See id. Therefore, for the same reasons stated for claim 1, we also
sustain the Examiner's rejection of claims 2-5.
Claim 6--19
In addition to the argument raised for claim 1, which we have found
unpersuasive, Appellants argue claim 6 is patentable because "W eiberle
does not disclose the use of a data frozen flag in the manner recited in Claim
6." Id. at 8. Specifically, claim 6 recites:
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Application 12/704,614
6. The method of Claim 5, wherein the step of performing
the calculations of the second path comprises the steps of:
performing the calculations of the second path using the
processor and the second data so long as the data frozen flag is
active; and
setting the data frozen flag to inactive if the first data
becomes ready for processing at any time during the performing
of the calculations of the second path.
Id. at 21 (Claims App.) (emphasis added). To evidence Weiberle discloses
those steps, the Examiner identifies paragraphs 29, 30, 33, 43, 54, 57-59.
Final Act. 4--5, Ans. 4. Reviewing those paragraphs, however, we are
unable to find support for the Examiner's associated findings.
Paragraph 29 discusses how the two execution units of the exemplary
embodiment are provided operands and how those operands are processed
prior to being supplied to the execution units. Paragraph 30 discusses how
the accuracy and security of the operands are safeguarded using error
detection. Paragraph 33 discusses how the execution units handle the
resulting data produced. Paragraph 43 discusses the classification of
programs. Paragraph 54 discusses the comparing process that occurs in
safety mode, after the calculations are performed. Of particular interest, in
that paragraph Weiberle states, "[i]f there is a difference [detected at the
comparator], the results will not be released and not written to the bus, but
written into an error register, for instance, or a flag or an error signal will be
generated in order to initiate a display or a corresponding error reaction."
Paragraphs 57-59 discuss how an alternative embodiment in which the
execution units share a single operand input operates similarly to the
previous described embodiment, which includes multiple operand inputs.
What is noticeably absent from any of the cited Weiberle paragraphs
is any suggestion of performing calculations of a path only if a flag is active
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and setting the same flag to inactive after determining another path is ready
for processing. At most, the paragraphs cited by the Examiner disclose
using a flag, in safety mode, to indicate that the redundant calculations do
not match because of an error. The flag is used to indicate the detection of
an error, which is unrelated to directing processor traffic via a first and
second path. Nor does the Examiner explain why a skilled artisan would
correlate the flag Weiberle discusses with the claimed "data frozen flag"
used by a processor to determine from which path it will receive data to
perform calculations.
Without such a disclosure, W eiberle fails to provide a preponderance
of the evidence to support the Examiner's anticipation finding for claim 6
and, as a result, we do not sustain the Examiner's rejection. Claims 7-19
likewise, either directly or indirectly, include limitations similar to claim 6
requiring the use of a flag, which is set to active or inactive based on
whether a path is ready for processing, to dictate from which path a
processor will receive data to perform calculations. Therefore, for the same
reasons discussed for claim 6, we do not sustain the anticipation rejections of
claims 7-19.
Claim 21
Claim 21 depends from claim 1, and adds:
the step of performing calculations of the first path
comprises performing the calculations of the first path via time
sampling at a first rate via the processor; and
the step of performing calculations of the second path
comprises performing calculations of the second path via time
sampling at a second rate via the processor, the second rate
being different from the first rate.
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Appeal Br. 28 (Claims App.). Appellants challenge the Examiner's finding
that Weiberle discloses the recited sampling. Id. at 10-11. In fact,
Appellants correctly point out that the Examiner fails to provide any analysis
regarding claim 21 in the Final Office Action. Id. Instead, the Examiner
states claim 21 is rejected for the same reasons discussed for claims 1-9, but
claims 1-9 do not include the same sampling limitations recited in claim 21.
Final Act. 7.
Nevertheless, in the Answer, the Examiner finds Weiberle teaches
time sampling at paragraphs 36, 46, 54, 55, and claims 26, 28, and 36. Ans.
3. In particular, the Examiner points to W eiberle' s description of
execution-time errors. Id. Having considered those paragraphs and claims
cited, we again are unable to find support for the Examiner's associated
findings regarding the limitations of claim 21. W eiberle teaches,
"[ e ]xecution-time errors within an ALU 1, 2 are detected if the result does
not arrive at the corresponding comparator unit and/or the corresponding
result registers or if it arrives too late and a comparison this takes place with
a partial result." Weiberle i-f 36. Rather than teaching the performance of
calculations of the first/second paths via time sampling at different
first/second rates, Weiberle's "execution-time error" detects whether
corresponding results arrive at an intended location within a defined
window. The Examiner does not explain how and/or why a skilled artisan
would understand the means for determining "execution-time errors"
necessarily involves time sampling of a first/second path at different
first/second rates. And, it is not readily apparent to us such a correlation
exists.
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In addition, W eiberle' s discussion regarding different timing rates is
discussed in the context of supplying operands to the execution units in
either the performance mode or safety mode. See W eiberle i-f 54, claims 26,
28, and 36. In the performance mode, only one execution unit is fed with a
corresponding operand with the following operand being fed to the parallel
execution unit "virtually simultaneously (in the same full cycle), i.e., in the
next half-cycle section." Id. i-f 54. In safety mode, "the operands are
supplied to the execution units using a full cycle, so that the same operand
will be supplied in each case and processed in the execution units in a
redundant manner." Id. i-f 58. Thus, in performance mode, two operands are
supplied to the execution units in a full cycle; whereas, in safety mode, a
single operand is supplied to the execution units in a full cycle. We do not
find W eiberle' s discussion of supplying operands to the execution units at
different rates to be supportive of the Examiner's finding Weiberle discloses
the steps of performing the calculations of the first/second paths via time
sampling at a different first/second rate via the processor, as claim 21
reqmres.
Given the above deficiencies, the Examiner has not shown, by a
preponderance of the evidence, W eiberle anticipates claim 21. Therefore,
we do not sustain the Examiner's rejection.
DECISION
The Examiner's decision to reject claims 1-5 is affirmed.
The Examiner's decision to reject claims 6-19 and 21 is reversed.
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Application 12/704,614
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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