Ex Parte Weirauch et al

Patent Trial and Appeal Board

Mar 18, 2013

11234483 (P.T.A.B. Mar. 18, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte STEVEN C. MILLER
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Appeal 2010-006960
Application 10/976,531
Technology Center 2100
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Before ALLEN R. MacDONALD, LYNNE E. PETTIGREW and
MIRIAM L. QUINN, Administrative Patent Judges.

QUINN, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) (2002) from a final
rejection of claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b).

We AFFIRM.
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STATEMENT OF THE CASE
Introduction
According to Appellant, the invention relates in general to computer
systems and memory processing, and, more particularly, to a system and
method for synchronizing distribution of transaction operations in a
computer system. (Spec. 1, ll. 2-5.)
Independent claim 1 is illustrative of the claimed subject matter and
reads as follows:
1. A method for synchronizing distribution of
transaction operations in a computer system,
comprising:
assigning a unique cache line of a memory
subsystem to each of a plurality of devices;
distributing by a monitoring unit a transaction
operation to each of the plurality of devices;
initially reading by the monitoring unit each
assigned cache line in response to distribution of the
transaction operation to each of the plurality of
devices;
performing the distributed transaction operations
at the plurality of devices;
for each device, reading its associated assigned
cache line of the memory subsystem in response to
completion of a respective transaction operation;
for each cache line read by the plurality of
devices, generating a cache invalidation message at the
memory subsystem;
counting at the monitoring unit the cache
invalidation messages to determine when the plurality
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of devices have completed their respective transaction
operations.
References
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Fry US 4,403,286 Sept. 6, 1983
Barnes US 4,412,303 Oct. 25, 1983
Cloutier US 5,892,962 Apr. 6, 1999
Williams US 6,327,668 B1 Dec. 4, 2001
Jim Handy, The Cache Memory Book 124, 156 (2
nd
ed., Academic Press
1998) (hereinafter “Handy”)
Rejections on Appeal
Claims 16 and 17 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Barnes. Ans. 3-5.
Claims 18-19 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Barnes and Handy, and further in view of Fry. Ans. 5-6.
Claims 1-3, 5, 6, and 10 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Barnes and further in view of Williams. Ans. 6-9.
Claims 7 and 8 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Barnes and further in view of Williams and Fry. Ans. 9-
10.
Claim 4 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Barnes in view of Williams, and further in view of
Cloutier. Ans. 10.
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Claims 9, 11, and 13-15 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Barnes in view of Williams, and further in view of
Handy. Ans. 11-14.
Claim 20 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Barnes and further in view of Handy. Ans. 15.

ISSUES
Based on Appellant’s arguments, the dispositive issues on appeal are
as follows:
(1) Did the Examiner err in rejecting independent claims 1,
11, and 16 under 35 U.S.C. § 103(a) because Barnes fails to teach or
suggest “initially reading by the monitoring unit each assigned cache
line in response to distribution of the transaction operation to each of
the plurality of devices,” as recited in claim 1, and commensurately
recited in claims 11 and 16 (App. Br. 9, 14, and 18)?
(2) Did the Examiner err in rejecting independent claims 1,
11, and 16 under 35 U.S.C. § 103(a) because Barnes fails to teach or
suggest “reading its associated assigned cache line of the memory
subsystem in response to completion of a respective transaction
operation,” as recited in claim 1, and commensurately recited in
claims 11 and 16 (App. Br. 9-10, 14, and 18)?
(3) Did the Examiner err in rejecting independent claims 1,
11, and 16 under 35 U.S.C. § 103(a) because Barnes fails to teach or
suggest “generating a cache invalidation message at the memory
subsystem,” as recited in claim 1, and commensurately recited in
claims 11 and 16 (App. Br. 10, 14, and 18)?
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(4) Did the Examiner err in rejecting independent claims 1
and 11 under 35 U.S.C. § 103(a) because neither Williams nor Barnes
teaches or suggests “counting at the monitoring unit the cache
invalidation messages to determine when the plurality of devices have
completed their respective transaction operations,” as recited in claim
1, and commensurately recited in claim 11 (App. Br. 14-15, Reply 5)?

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellant’s
contentions that the Examiner has erred. Further, we have reviewed the
Examiner’s response to Appellant’s arguments.
Issue of Reading by the Monitoring Unit – Claims 1, 11, and 16
Independent claim 1 recites the step of “initially reading by the
monitoring unit each assigned cache line in response to distribution of the
transaction operation to each of the plurality of devices.” Independent claim
16 recites the same limitation, albeit in the form of means-plus-function
language. Independent claim 11, a system claim, recites that “the
monitoring unit [is] operable to read each cache line upon distribution of the
transaction operations.” The Examiner finds that Barnes teaches or suggests
this limitation. Ans. 4, 7, and 12. Barnes teaches a coordinator that
communicates with the support processor to load jobs into and results out of
the database memory and that communicates with the processors in order to
provide synchronization and control when all processors are to operate in
parallel on a particular piece of data or at a particular step in the program.
Barnes, col. 6 ll. 61-67.
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Appellant contends that Barnes does not teach the limitation-at-issue
because the coordinator in Barnes does not perform the reading function.
App. Br. 9. Specifically, Appellant argues that the Barnes’ processors and
the memory system (database memory 17 and database controller 19)
perform the reading – not the coordinator. Id. In Appellant’s view, no
reading of the extended memory is performed until a processor executes an
instruction, failing thus to teach “initially reading by the monitoring unit . . .
in response to distribution of the transaction operation . . . .” Id. Since the
coordinator in Barnes “cannot read a cache line . . . . it cannot read the cache
lines associated with each device in response to distribution of a transaction
operation to each device.” App. Br. 11.
The Examiner responds that Barnes teaches or suggests that reading is
performed by the claimed monitoring unit because the Barnes’ coordinator is
used to direct control over the reading and writing of data, even if the
coordinator itself does not perform all the functions needed to actually
complete each read process. Ans. 16. Therefore, the reading is done “by the
coordinator” even though part of the reading process may be performed by
other devices as well. Id. The Examiner further points out that the rejection
over Barnes is not limited to the coordinator there disclosed; the rejection is
made over a combination of components in Barnes together with the
coordinator, namely the support processor and database memory controller,
which all work together to move data into the appropriate location based on
the coordinator’s control. Ans. 16 (citing Barnes, fig.1, col. 6 ll. 61-67, and
col.7 ll. 4-13.); Ans. 17 (adding that the rejection does not constrain the
interpretation of “monitoring unit” to the coordinator, but rather it references
other components the coordinator controls, such as the support processor).
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In the Reply Brief, Appellant admits that the coordinator “issues a
descriptor to a database memory controller 19 in order for the database
memory controller 19 to pass data and program instructions for a run from
the database memory 17 to an extended memory module 13.” Reply 2
(citing Barnes, col. 12 ll. 39-48). Appellant further argues that although
Barnes discloses there may be a mapping scheme between processors and
extended memory modules, Barnes “fails to disclose that there is a different
cache line assigned for each processor as required . . . .” Reply 3.
We agree with the Examiner that Barnes teaches or suggests this
limitation. As the Examiner correctly states, Barnes teaches a combination
of devices that work together to load programs and data into extended
memory. See Barnes, col. 6 l. 61 – col.7 l. 13. At least one of those devices,
the database memory controller, is disclosed as performing a reading
operation. For example, we find that in column 12, lines 39-52, to which
Appellant directed us, Barnes teaches that the database memory controller
reads the database memory to ensure that the descriptors match those
requested by the coordinator. See Barnes, col. 12 ll. 39-52. The data stored
in the database memory is passed to the extended memory module at the
direction of the controller. Id. Furthermore, as Appellant admits, Barnes
teaches that the database memory is mapped. Reply 3; Barnes, col. 12 ll. 33-
39. That map dictates the storage location of the job data, such that, as the
database memory controller passes the data to the extended memory, each
mapped memory location is allocated to each processor. Barnes col. 3 ll. 31-
47.
We, therefore, conclude that the Examiner did not err in finding that
Barnes teaches a monitoring unit (a combination of the coordinator, support
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processor, and database memory controller) that reads “each assigned cache
line in response to distribution of the transaction operation to each of the
plurality of devices,” as required by claims 1 and 16, and commensurately
recited in claim 11.
Issue of Reading in Response to Completion of a Transaction Operation –
Claims 1, 11, and 16
Independent claim 1 recites the step of “for each device, reading its
associated assigned cache line of the memory subsystem in response to
completion of a respective transaction operation.” Independent claim 16
recites a “means for reading the associated cache line by each of the plurality
of devices in response to completion of the transaction operation.” Claim 11
similarly recites this limitation. The Examiner finds that Barnes teaches or
suggests this limitation as it discloses that memory lines are read upon
completion of a respective transaction operation to fetch the next transaction
operation. Ans. 4, 7, and 12.
Appellant contends that Barnes fails to teach this limitation because
each processor does not read the memory after completing a transaction.
App. Br. 9-10. Specifically, Appellant argues that after a processor
completes a transaction, it places the result in the respective memory
module, and it halts further processing. App. Br. 10. “No reading of the
extended memory 13 is performed at this time by any processor 29 let alone
in response to completion of a respective instruction.” Id.
The Examiner responds that each processor reads the next instruction
when it has completed the current instruction and the coordinator
acknowledges that the transaction is complete. Ans. 17. Therefore, the
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reading of the next instruction “happens in response to all the previous steps
pertaining to the previous instruction being performed, including completion
of a respective transaction operation.” Ans. 18 (citing Barnes, col. 5 ll. 3-12,
col. 6 ll. 27-31) (emphasis added).
Appellant in reply argues that the next instruction comes from a
different storage location in the extended memory module. Reply 4.
Appellant further repeats the argument that since there is no “first reading”
of the next instruction, there is no “second reading.” Reply 4.
We concur with the Examiner that Barnes teaches this limitation.
Barnes teaches that the processors begin their next instruction after
completing the first instruction. Barnes, col. 5 ll. 9-13. This next instruction
is in the memory module assigned to that processor. See Barnes, col. 4 ll.
42-47. Therefore, Appellant’s argument that the next instruction comes
from a different memory module is unpersuasive. Furthermore, as correctly
noted by the Examiner, the processor reads the next instruction upon
completion of the previous instruction. Ans. 18. The broadest reasonable
interpretation of the claim language does not preclude the processor from
reading that next instruction after the coordinator issues a GO signal for
continued processing. Appellant’s arguments to the contrary are, therefore,
unpersuasive.
Accordingly, we find that the Examiner did not err in finding that
Barnes teaches or suggests this limitation.
Issue of Generating a Cache Invalidation Message – Claims 1, 11, and 16
Independent claim 1 recites the step of “for each cache line read by
the plurality of devices, generating a cache invalidation message at the
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memory subsystem.” Claims 11 and 16 recite similar limitations. The
Examiner finds that Barnes teaches this limitation by disclosing that a signal
is generated by the coordinator “signifying a message that one of the
processors [has] completed their instruction.” Ans. 4-5. The Examiner
construes the term “cache invalidation message” to mean “a message that the
processor has completed the instruction read from an assigned line of
cache.” Ans. 4.
Without challenging the Examiner’s construction, Appellant contends
that Barnes does not teach this limitation. App. Br. 10. Specifically,
Appellant argues that Barnes’ processors issue an “I got here” flag to the
coordinator upon completing their instruction. Id. However, in Appellant’s
view, the claimed devices “merely read their assigned cache line and do not
issue any signals to the monitoring unit.” App. Br. 10. Appellant further
argues that Barnes teaches away from this limitation by requiring that each
processor issue a completion flag directly to the coordinator upon
completing its instruction, because the flag is not generated in response to
any reading of an assigned cache line by the processors, as required by the
claims. App. Br. 11.
The Examiner responds that the coordinator is part of the claimed
memory subsystem, and that it issues the cache invalidation message. Ans.
19. The Examiner relies on the broadest reasonable interpretation given to
the term “cache invalidation message” to find that the coordinator issues the
message after a cache line is read and the operation pertaining to that cache
line is complete. Ans. 19. The Examiner further points out that Barnes does
not teach away from this limitation by first requiring that processors issue an
“I got here” flag upon completion of a transaction. Ans. 19. The Examiner
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finds that Barnes teaches that each “I got here” flag causes the coordinator to
generate a corresponding new signal, and all the new signals are summed
using an AND operation to determine that all of the processors are ready to
receive the next operation. Ans. 19. In reply, Appellant repeats that the “I
got here” messages are generated by the processors and not by either the
coordinator or the extended memory module. Reply 4.
We do not agree with Appellant’s conclusions. The claim language
requires that the cache invalidation message is generated at the memory
subsystem, which the Examiner finds is met by the structure of the controller
that receives from the processor array the “I got here” messages and that
creates a corresponding new signal 61 (Barnes, fig.4). Ans. 4-5. Therefore,
we are not persuaded by Appellant’s arguments that the processors generate
the claimed signal, and not the coordinator. Furthermore, as the Examiner
correctly notes, the coordinator generates this new signal 61 each time the
processors have completed the current operation pertaining to the assigned
cache line. Ans. 19. As such, we find no error in the Examiner’s finding
that Barnes teaches or suggests “generating a cache invalidation message at
the memory subsystem,” where the “cache invalidation message” is a
message that the processor has completed the instruction read from an
assigned line of cache.
Issue of Counting the Cache Invalidation Messages – Claims 1 and 11
Appellant contends that Williams and Barnes fail to teach the
limitation of “counting at the monitoring unit the cache invalidation
messages to determine when the plurality of devices have completed their
respective transaction operations,” as recited in claim 1 and commensurately
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recited in claim 11. Specifically, Appellant argues that the instruction
counter disclosed in Williams provides a progress indication every n counts
to identify how long it takes for an instruction to be processed. App. Br. 14.
Williams’ counter, however, does not “determine when the plurality of
devices have completed their respective transactions as required by the
claimed invention.” App. Br. 14-15.
The Examiner responds that Williams discloses the act of counting to
synchronize processing steps, and that Barnes discloses the act of receiving
the invalidation messages to determine when each processor has completed
its operation transaction. Ans. 20. In Barnes, the Examiner points out, the
invalidation messages are summed using an AND operation, instead of using
a counter. Id.
Appellant in reply argues that Barnes “cannot count the number of
invalidation messages it receives.” Reply 5. Barnes’ device uses an AND
logic to determine when all of the processors have finished and not how
many processors have finished. Reply 5 (emphasis added).
We do not agree with Appellant’s conclusion that the Examiner erred
in concluding that the combination of Barnes and Williams teaches this
limitation. The claim language requires a count, but only to “determine
when the plurality of devices have completed.” As such, we agree with the
Examiner’s findings that Barnes’ device, by summing (using an AND gate)
the received invalidation messages, teaches the determination of when the
plurality of devices have completed their respective transaction operations
(Ans. 20), and that Williams’ disclosure of a counter is a known technique
for maintaining synchronization of processing steps (Ans. 8).
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Accordingly, we find that the Examiner did not err in finding that the
combination of Barnes and Williams teaches or suggests this limitation.
CONCLUSION
On the record before us, we conclude that the Examiner has not erred
in rejecting: (1) claims 16 and 17 under 35 U.S.C. § 103(a) as being
unpatentable over Barnes; (2) claims 18 and 19 under 35 U.S.C. § 103(a) as
being unpatentable over Barnes, Handy, and Fry; (3) claims 1-3, 5, 6, and 10
under 35 U.S.C. § 103(a) as being unpatentable over Barnes and Williams;
(4) claims 7 and 8 under 35 U.S.C. § 103(a) as being unpatentable over
Barnes, Williams and Fry; (5) claim 4 under 35 U.S.C. § 103(a) as being
unpatentable over Barnes, Williams, and Cloutier; (6) claims 9, 11, and 13-
15 under 35 U.S.C. § 103(a) as being unpatentable over Barnes, Williams,
and Handy; and (7) claim 20 under 35 U.S.C. § 103(a) as being unpatentable
over Barnes and Handy.
DECISION
We affirm the Examiner’s decision to reject claims 1-20 under
35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

ELD