Ex Parte Wei et al

Patent Trial and Appeal Board

Apr 22, 2016

11936855 (P.T.A.B. Apr. 22, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
111936,855 11108/2007 Andy Wei
109712 7590 04/26/2016
Advanced Micro Devices, Inc,
c/o Davidson Sheehan LLP
700 Lavaca
Suite 1400-2323
Austin, TX 78701
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
1458-DE0862 1601
EXAMINER
MIYOSHI, JESSEY
ART UNIT PAPER NUMBER
2896
NOTIFICATION DATE DELIVERY MODE
04/26/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docketing@ds-patent.com
caitlin.taylor@ds-patent.com
beatrice. zepeda@ds-patent.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ANDY WEI, THORSTEN KAMMLER,
ROMAN BOSCHKE, and CASEY SCOTT
Appeal2014-001625
Application 11/936,855
Technology Center 2800
Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and
JAMES C. HOUSEL, Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF CASE
Appellants2 appeal the Examiner's decision to reject claims 1-5 and
21-38. We have jurisdiction under 35 U.S.C. §§ 6(b) and 134(a).
We REVERSE.
1 In our opinion below, we refer to Final Office Action mailed January 29,
2013 (Final), and the Appeal Brief filed June 27, 2013 (Appeal Br.).
2 Appellants identify the real party of interest as Advanced Micro Devices,
Inc. Appeal Br. 1.
Appeal2014-001625
Application 11/936,855
The claims are directed to a semiconductor device including a
transistor formed above a buried insulating layer (see, e.g., claims 1, 26, and
32). The transistor includes drain and source regions in a semiconductor
material. Id.
All the claims require the semiconductor material have either a
tapered edge profile that is widest at the buried insulating layer (see e.g.,
claims 1 and 32) or a trapezoidal profile along an edge defined between the
gate electrode of the transistor and the buried insulating layer (see e.g., claim
26). We reproduce an annotated Figure 2e from Appellants' Brief that
identifies the location of the tapered edge profile below:
Edge wiU1
Tape;red
" . "
Prorne
i. 4,3
')£.f_~~~ ,l,·as &1"2· ";n., ~th
~ .. ~"~··
FJG,2
Ge's Figure 2 is a cross-section of a first embodiment of a semiconductor
device 10 annotated to show the location of a tapered profile
Figure 2 shows isolation region 28 as filled with dielectric material.
Figure 2 also shows a thin film layer 44 deposited above the isolation region.
The Examiner acknowledges that Figure 2 does not show film 44,
which the Examiner finds is a strain-inducing dielectric layer, along the edge
of the semiconductor material 16, 18 down to the buried insulating layer 14
as required by the claims. But the Examiner finds that Ge teaches forming
the isolation region from nothing using the mesa method. Final 2.
According to the Examiner, when forming the isolation region from nothing,
patents, the Examiner's failure to provide notice of non-compliance was not
harmful to Appellants.
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Appeal2014-001625
Application 11/936,855
the edge of semiconductor material 16, 18 would be tapered as evidenced by
Figures 1 and 2, and film 44 would extend to buried insulating layer 14
adjacent to the drain and source regions 38, 36 as required by the claim.
Final 2-3.
Ge describes forming the isolation regions 28 by a number of different
processes including standard shallow trench isolation (STI) or local
oxidation of silicon (LOCOS) as well as from other materials such as silicon
nitride. Ge, col. 4, 11. 18-28. Although Figure 2 may reflect the profile of
the semiconductor material 16, 18 that results from one or more of these
processes, it is less clear that it reflects the profile that would result when
forming the isolation region 28 from nothing by a mesa method. Ge
provides no details of the mesa process-Figures 1 and 2 only depict filled
isolation regions 28 that would not be made by the mesa method-and the
Examiner provides no technical reasoning, much less evidence, supporting a
finding that a tapered profile would necessarily result from the mesa process.
Ge voices no concern about the profile of the semiconductor layers 16, 18.
Moreover, Ge does not "describe" within the meaning of§ 102
depositing the film 44 along the mesa-formed edge so it extends to the
buried insulating layer. Figure 2 merely depicts filled isolation regions with
the thin film 44 deposited over the top. Ge describes using a trench liner,
which is not shown in the Figures, that induces stress on layer 16, 18, and
discloses forming the film layer 44 over the source/drain regions 24, 26, 36,
and/or 38, but there is no description of further extending the film layer 44
into the trench. Nor does the Examiner point to any convincing evidence
that the mesa method would necessarily result in layer 44 extending along a
tapered edge to the buried insulation layer.
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Appeal2014-001625
Application 11/936,855
We emphasize that the rejection is based upon anticipation and, hence,
Ge must describe either expressly or inherently the structure recited in the
claims. The Examiner has not established that Ge so describes the claimed
structure.
Because the Examiner relies upon Ge in the same manner in all the
rejections, all the rejections contain the deficiencies discussed above.
CONCLUSION
We do not sustain the Examiner's rejections.
DECISION
The Examiner's decision is reversed.
REVERSED
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