Ex Parte Watts et al

Board of Patent Appeals and Interferences

Sep 16, 2010

11123464 (B.P.A.I. Sep. 16, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte LAVAUGHN F. WATTS JR.
and STEVEN J. WALLACE
____________

Appeal 2009-009202
Application 11/123,464
Technology Center 2100
____________

Before JOHN A. JEFFERY, JOSEPH L. DIXON, and JAMES R. HUGHES,
Administrative Patent Judges.

DIXON, Administrative Patent Judge.

DECISION ON APPEAL1

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.

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The Appellants appeal under 35 U.S.C. § 134(a) from a Final rejection
of claims 22-44. Claims 1-21 have been canceled. We have jurisdiction
under 35 U.S.C. § 6(b).
We Affirm.

I. STATEMENT OF THE CASE
The Invention
The invention at issue on appeal relates to a method and apparatus for
managing the power of a central processing unit (CPU) by changing the
clock time of the CPU based on the activity-level within of the CPU of a
portable computer (Abs.).
The Illustrative Claims
Claims 22, 33, and 44, illustrative claims, read as follows:
22. A method, comprising the steps of:
determining a work load level associated with a processor; and
using results of said determining for reducing power
consumption associated with said processor as said work load
level decreases.
33. A method, comprising the steps of:
determining a work load level associated with a processor; and
using results of said determining for increasing power
consumption associated with said processor as said work load
level increases.
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44. A method, comprising the steps of:
determining a work load level associated with a processor; and
using results of said determining for reducing power
consumption associated with said processor as said work load
level decreases and increasing power consumption associated
with said processor as said work load level increases.
The References
The Examiner relies on the following references as evidence:
Sheets US 4,670,837 Jun. 12, 1987
Fairbanks US 5,021,679 Jun. 4, 1991

The Rejections
The following rejections are before us for review:
Claims 22-44 stand provisionally rejected under non-statutory
non-obviousness-type double patenting as being unpatentable over the
claims 24-47 of co-pending Application No. 11/137,032, and claims 22-
44 of co-pending Application No. 11/123,440. (Both having the same
effective filing date as the instant application).
Claims 22-32 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Sheets.
Claims 33 and 42-44 stand rejected under 35 U.S.C. § 102(e) as
being anticipated by Fairbanks.
Claims 34-41 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Sheets and Fairbanks.
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Only those arguments actually made by the Appellants has been
considered in this decision. Arguments which the Appellants could have
made but chose not to make in the Briefs have not been considered and are
deemed to be waived. See 37 C.F.R. § 41.37 (c)(1)(vii) (2008).

II. ISSUES
1. Has the Examiner erred in identifying that claims 22-44 stand
rejected under provisional nonstatutory obviousness-type double patenting
as being unpatentable over claims 24-47 of copending Application No.
11/137,032, and claims 22-44 of co-pending Application No. 11/123,440
(now claims 1-23 of US 7,392,416 B2).
2. Has the Examiner erred in identifying that Sheets discloses
“determining a work load level associated with a processor; and using results
of said determining for reducing power consumption associated with said
processor as said work load level decreases.” as recited in claim 22?
3. Has the Examiner erred in identifying that Fairbanks discloses
“determining a work load level associated with a processor; and using results
of said determining for increasing power consumption associated with said
processor as said work load level increases.” as recited in claim 33, and
“using results of said determining for reducing power consumption
associated with said processor as said work load level decreases and
increasing power consumption associated with said processor as said work
load level increases.”, as recited in claims 44?
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4. Has the Examiner erred in identifying that the combination of
Sheets and Fairbanks teaches and fairly suggests claimed limitations as
recited in claims 34-41, in particular, “an amount of said increasing power
consumption is proportional to the increase of said work load level”, recited
in claim 34, and “said increasing power consumption continues until one of
a) no increase in work load level is detected over a previous determination of
work load level; and b) said processor has reached its maximum power
consumption level;” recited in claim 37?
III. PRINCIPLES OF LAW
Scope of Claim
During prosecution before the USPTO, claims are to be given their
broadest reasonable interpretation, and the scope of a claim cannot be
narrowed by reading disclosed limitations into the claim. See In re Morris,
127 F.3d 1048, 1054 (Fed. Cir. 1997). The Office must apply the broadest
reasonable meaning to the claim language, taking into account any
definitions presented in the specification. In re Am. Acad. of Sci. Tech Ctr.,
367 F.3d 1359, 1364 (Fed. Cir. 2004) (citing In re Bass, 314 F.3d 575, 577
(Fed. Cir. 2002)).
“Giving claims their broadest reasonable construction ‘serves the
public interest by reducing the possibility that claims, finally allowed, will
be given broader scope than is justified.’” Id. (quoting In re Yamamoto, 740
F.2d 1569, 1571 (Fed. Cir. 1984)). “Construing claims broadly during
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prosecution is not unfair to the applicant . . . because the applicant has the
opportunity to amend the claims to obtain more precise claim coverage.” Id.
“The PTO's construction here, though certainly broad, is unreasonably
broad. The broadest construction rubric coupled with the term “comprising”
does not give the PTO an unfettered license to interpret claims to embrace
anything remotely related to the claimed invention. Rather, claims should
always be read in light of the specification and teachings in the underlying
patent. See Schriber-Schroth Co. v. Cleveland Trust Co., 311 U.S. 211, 217,
61 S.Ct. 235, 85 L.Ed. 132 (1940).” (In re Suitco Surface, Inc., No. 2009-
1418, 2010 WL 1462294, at *4 (Fed. Cir. 2010).)
Nonstatutory Obviousness-type Double Patenting
A nonstatutory obviousness-type double patenting rejection is
appropriate where the conflicting claims are not identical, but at least one
examined application claim is not patentably distinct from the reference
claim(s) because the examined application claim is either anticipated by, or
would have been obvious over, the reference claim(s). See e.g., In re Berg,
140 F.3d 1428 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046 (Fed. Cir.
1993); In re Longi, 759 F.2d 887 (Fed. Cir. 1985).
Anticipation
Analysis of whether a claim is patentable over the prior art under 35
U.S.C. § 102 begins with a determination of the scope of the claim. We
determine the scope of the claims in patent applications not solely on the
basis of the claim language, but upon giving claims their broadest reasonable
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construction in light of the Specification as it would be interpreted by one of
ordinary skill in the art. In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d at 1364.
The properly interpreted claim must then be compared with the prior art.
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citation omitted).
Obviousness
“Obviousness is a question of law based on underlying findings of
fact.” In re Kubin, 561 F.3d 1351, 1355 (Fed. Cir. 2009). The underlying
factual inquiries are: (1) the scope and content of the prior art, (2) the
differences between the prior art and the claims at issue, (3) the level of
ordinary skill in the pertinent art, and (4) secondary considerations of
nonobviousness. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007)
(citation omitted).

IV. FINDINGS OF FACT
The following findings of fact (FFs) are supported by a preponderance
of the evidence.
Sheets
1. Sheets discloses that a method and microprocessor-based
system for conserving power by adjusting the operating clock frequency
upon determining the processing load:
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The magnitude of power consumed by a MOS device at a given
voltage is substantially directly proportional to the frequency at
which the device is operated. In the case of microprocessor 101,
which is a relatively complex MOS device, the duration of each
execution cycle is defined by the signal received at a CLK
terminal. In accordance with the present exemplary
embodiment of the invention, a digital, voltage-controlled
oscillator (VCO) 102 transmits the cycle-defining clock signal.
Upon determining the amount of processing required at any
given time, microprocessor 101 computes an operating
frequency that is sufficient to meet the offered processing load.
Microprocessor 101, which communicates with VCO 102 via
data bus 104, address bus 105 and conductor 106 in the same
manner as with RAM 108 or I/O port 109, writes a digital word
defined by the computed frequency via data bus 104 to VCO
102. VCO 102 gradually adjusts the frequency of the clock
signal transmitted to microprocessor 101 to the computed
frequency in response to the digital word. Reducing the clock
frequency reduces the power consumed by microprocessor 101
and, by reducing the required access rate to the associated
devices, i.e., ROM 107, RAM 108, and I/O port 109, also
reduces the power consumed by those devices. The power
reduction is substantially directly proportional to the reduction
of the clock frequency.

(col. 2, l. 48-col. 3 l. 6) (Emphases added).

2. Sheets further teaches the real time frequency computing:
In system 100, the timing of real-time events is controlled by
microprocessor 101 in response to interrupt signals received at
an INT terminal from a fixed-frequency oscillator 103. For
example, microprocessor 101 repeats the process of computing
the required frequency based on the processing load and
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writing a digital word to digital VCO 102 at regular intervals
as defined by the interrupt signals from fixed oscillator 103. In
the present embodiment, microprocessor 101 determines its
processing load to control the VCO 102 clock frequency at any
given time by using a linear regression.
(col. 3, ll. 8-21) (Emphases added).
3. Sheets also discloses either a real-time continuous clock
frequency or a discrete clock frequency may be used based on either the
processing backlog, the activity on data bus and address bus (current
processing load) or historical activity records:
Rather than computing the frequency based on the processing
backlog, the activity on data bus 104 and address bus 105
could be monitored and then used as a basis for determining
the required frequency. Instead of using a continuously
variable-frequency clock, selections can be made from a small
number of discrete frequencies. For example, in a battery-
powered personal computer with an operating system which
includes a sleep state, the microprocessor CPU could be
operated at a low frequency sufficient to keep any dynamic
logic refreshed, e.g., 500 kilohertz, when the operating system
is in the sleep state, and the frequency could then be increased
to a nominal operating frequency, e.g., 10 megahertz, when
wakeup occurs. In some applications, the desired clock
frequency could be determined based on historical activity
records rather than in real time.

(col. 4, l. 58-col. 5, l. 6) (Emphases added).

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Fairbanks
4. Fairbanks discloses a method and system for selectively
changing the clock frequencies in accordance with the processing loads:
In certain tasks performed by a computer system, such as word
processing, it is possible to operate the system clock at a slower
clock rate than is required for computational tasks. . . Thus by
operating at a slower clock frequency and lower voltage the
performance of the system is not degraded from the user's
perspective and the power consumed is reduced. Similarly, if
the system clock is operating at a lower frequency, the devices
utilized in the system may also be operated at a lower voltage
since the reduced voltage will still be adequate to provide
switching at the lower frequency . . . it has been found that
quite adequate performance may be achieved by using a VDD
of approximately 3 volts and a 2.3 mHz system clock frequency
to process information in the word processing mode of
operation. However, when the mode of operation of the
computer involves the computation of numerical data, it is
desirable, under most circumstances, to perform that function
quickly. Accordingly, in the computational mode the power
supply output is changed from 3 volts to 5 volts and the system
clock frequency changed from 2.3 mHz to 6.6 mHz. Under these
latter conditions the maximum speed of processing is achieved.

(col. 2, ll. 6-36) (Emphases added).

V. ANALYSIS
The Appellants have the opportunity on appeal to the Board of Patent
Appeals and Interferences (BPAI) to demonstrate error in the Examiner’s
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position. See In re Kahn, 441 F.3d 977, 985-86 (Fed. Cir. 2006) (citing In re
Rouffet, 149 F.3d 1350, 1355 (Fed. Cir. 1998)).
The Examiner sets forth a detailed explanation of a reasoned
conclusion of unpatentability in the Examiner’s Answer. Therefore, we look
to the Appellants’ Brief to show error in the proffered reasoned conclusion.
Id.
Grouping of Claims
The Appellants have elected to argue claims 24-32 together as a
group 1 (App. Br. 8), and claims 33, and 42-44 together as a group 2 (App.
Br. 11). Therefore, we select independent claim 24 as the representative
claim for the group 1, and independent claims 33 and 44 as the
representative claims for the group 2, and we will address the Appellants’
arguments with respect thereto. 37 C.F.R. § 41.37(c)(1)(vii). See In re
Nielson, 816 F.2d 1567, 1572 (Fed. Cir. 1987).

Nonstatutory Obviousness-type Double Patenting
ISSUE 1
With respect to claims 22-44, the Appellants contend that the
Examiner has not appropriately compared claims 22-44 of the instant
invention with claims 24-47 of copending Application 11/137,032. In
particular, claim 22 of copending Application 11/137, 032 only teaches the
limitations of determining temperature and a work load level associated with
a processor in claim 24 (App. Br. 20). (We further note that since both
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applications have the same effective priority date of Oct. 30, 1989, neither is
deemed to be an earlier filed application. Accordingly, the provisional
obviousness-type double patenting rejection is ripe for decision. Compare
Ex parte Moncla, No. 2009-006448, 2010 WL 2543659 (BPAI, June 22,
2010) (precedential), available at
http://www.uspto.gov/ip/boards/bpai/decisions/prec/fd09006448.pdf (noting
that, under the circumstances of that case, it was premature for the Board to
address the Examiner’s provisional obviousness-type double patenting
rejection).
We disagree with the Appellants’ contentions. Claim 24 of copending
Application 11/137,032 read as follows:
24. A method, comprising the steps of:
determining temperature and a work load level associated with
a processor; and
using results of said determining for reducing power
consumption associated with said processor as said work load
level decreases.
As we are comparing the representative claims of copending
Applications with claim 22 of the instant invention, we find that the claim
language in claim 24 of copending Application 11/137,032 encompasses the
claim language in claim 24 of the instant application. In fact, we find that
only difference is “temperature” recited in claim 24 of copending
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Application 11/137,032. Thus, it is clear to us that the provisional
nonstatutory obviousness-type double patenting rejection is appropriate
where the conflicting claims are not identical, but where some claims are not
patentably distinct from the reference claims because the examined
application claims are anticipated, or would have been obvious over claims
24, 35, and 44 of copending Application 11/137,032. (See e.g., In re Berg,
140 F.3d 1428 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046 (Fed. Cir.
1993); and In re Longi, 759 F.2d 887 (Fed. Cir. 1985)).
With respect to claims 22-44, the Appellants contend that the
Examiner has not appropriately compared claims 22-44 of the instant
invention with claims 22-44 of co-pending Application No. 11/123,440.
(App. Br. 20). At the outset we note that copending Application 11/123,440
is now US 7,392,416 B2. Therefore, the rejection is now a nonstatutory
obviousness-type double patenting rejection based upon the patent. Claim
22 of copending Application No. 11/123,440 (now claim 1 of US 7,392,416
B2) reads as follows:
1. A method, comprising the steps of:
detecting activity associated with a processor;
comparing an amount of detected activity with an amount of
detected activity from a previous detecting of activity
associated with said processor; and
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using results of said comparing for reducing power
consumption associated with said processor if said amount of
detected activity is a decrease over an amount of detected
activity from a previous determination.
We note that the claim language “detecting” and “comparing”, and
“activity” recited in claim 22 of copending application No. 11/123,440 (now
claim 1 of US 7,392,416 B2) is different from claimed limitations of
“determining” and “work load level” recited in claim 22 of the instant
application. However, the claims themselves do not define the argued terms.
Therefore, we must construe the terms broadly, yet reasonably. In light of
the breadth of Appellants’ Specification, we broadly, but reasonably
construe the claimed “work load level” as any processing load or activity or
load associated with a processor. We also broadly, but reasonably construe
the claimed “determining” as ascertaining after reasoning and/or observing
or deciding. We compare the steps of detecting of the instant invention and
the representative claims of copending Application No. 11/123,440 (now US
7,392,416 B2). We find that the reference claims 22-44 of copending
application No. 11/123,440 (now claims 1-23 of US 7,392,416 B2) contain
broader steps of determining than the instant invention, which uses different
wording, but also describe how to determine the temperature and activity
(work load level). As such, we conclude that the nonstatutory obviousness-
type double patenting rejection is appropriate where the conflicting claims
are not identical, but are not patentably distinct from the reference (Id.).
Accordingly, we sustain the Examiner’s nonstatutory obviousness-
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type double patenting rejections.

35 U.S.C. § 102 Rejections
ISSUE 2
With respect to claim 22, the Appellants contend that Sheets teaches a
frequency predetermined “for a particular yet to be accomplished job tasks”
(App. Br. 5). According to the Appellants, “to the extent Sheets lowers the
frequency of clock signals being sent to microprocessor 101, such lowered
frequency is PREDETERMINED and is in response to reliance on a
predetermined job table and NOT-in response to ‘reducing power
consumption associated with said processor As said work load level
decreases’, as required by Claim 22.” (Id.). In addition, “Sheets changes its
frequency based on anticipated program, task or job changes, not in response
to the work load level decreasing.” and “there is no real-time power saving
provided by Sheets.” (Id. 7).
We disagree with the Appellants’ contentions. First, whether or not
the lowered clock frequency is predetermined as well as real-time power
saving is not a limitation in claim 22. Moreover, we find Sheets teaches
determining the processing load (work load) of a processor and then
adjusting the operating frequency to conserve the power consumption (FF 2).
We also find Sheets further teaches that the timing of computing the
processing load by the processor can be any time (FF 3), which includes the
real time. Furthermore, we find that the processing load can be determined
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by determining the activity on the data bus and the address bus that is the
current processing load for the processor (offered processing load), e.g.,
when the wakeup state of the CPU/operation system changes to the sleep
state, the clock frequency will change from 10 megahertz to 500 kilohertz so
as to reduce the power consumption (FF 3). Therefore, Sheets teaches the
limitation of adjusting the clock frequency in real time, thus, the power
consumption of the processor decreases as the processing load
changes/decreases.
Accordingly, we sustain the Examiner’s anticipation rejection of
claim 22. We further sustain the Examiner’s anticipation rejection of
dependent claims 27-32, which have not been separately argued, and these
claims therefore fall with their base claims. 37 C.F.R. § 41.37 (c)(1)(vii).
See In re Nielson, 816 F.2d at 1572.
With respect to claim 23, the Appellants contend that “’[t]he offered’
processing load is the anticipated load of a program requested to be run—
there is nothing ‘proportional’ about it.” (App. Br. 8).
We disagree with the Appellants’ contention. We find Sheets
expressly teaches that the reduction of the power consumption is directly
proportional to the reduced clock frequency at which the CPU (FF 1) and
the reduced clock frequency is determined by determining the processing
load such as the activity of the data bus and the address bus (FF 3).
Therefore, the decrease of the work load results of decrease of clock
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frequency of the CPU that is directly proportional to the reduction of the
power consumption.
Accordingly, we sustain the Examiner’s anticipation rejection of
claim 23.
With respect to claim 24, the Appellants contend “to the extent Sheets
lowers the frequency of clock signals being sent to microprocessor 101, such
lowered frequency is PREDETERMINED and is in response to reliance on a
predetermined job table and NOT-‘accomplished in incremental steps’, as
required by Claim 24.” (App. Br. 8-9).
We disagree with the Appellants’ contention. We find Sheets teaches
that the clock frequency can be changed to a small number of discrete
frequencies (FF 3) and the power consumption is directly proportional to the
clock frequency (FF 1), and thus, the changes (reductions) of power
consumption are accomplished in incremental steps.
Accordingly, we sustain the Examiner’s anticipation rejection of
claim 24.
With respect to claims 25-26, the Appellants contend that “to the
extent Sheets lowers the frequency of clock signals being sent to
microprocessor 101, such lowered frequency is PREDETERMINED and is
in response to reliance on a predetermined job table and NOT-a reduction in
power consumption that continues until one of: a) no decrease in work
load level is detected over a previous determination of work load level;
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and b) said processor has reached its minimum power consumption
level” (App. Br. 10).
First, the claim language does not preclude such that a predetermined
frequency is for a predetermined work load level. In addition, we note that
there is only one of the two limitations needed to be found in the prior art
teachings, and step A of claim 26 contains the same language as that of
claim 25. Furthermore, we find Sheets teaches that the lowest power
consumption corresponding the lowest frequency (FF 1) is reached when the
CPU/operating system is in sleep state operated at 500 kilohertz, and the
consumption level increases until CPU is in wakeup state, the operating
frequency is 10 megahertz (FF 3). In our view, Sheets’ teaching the process
that the operating clock frequency changes from the wakeup state (higher
power consumption level) to the sleep state (lower power consumption
level) reads on the claimed language of claim 26. This reduction of the
power consumption continues while the clock frequency decreases to 500
kilohertz where no decrease in work load level is detected over a
predetermined work load level (the sleep state is detected/reached). Finally,
we find Sheets teaches that the processor has reached its minimum power
consumption level at the sleep mode (FF 3). We, therefore, conclude that
Sheets teaches the limitation of claims 25-26.
Accordingly, we sustain the Examiner’s anticipation rejection of
claims 25-26.

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ISSUE 3
With respect to claims 33 and 44, the Appellants contend that
Fairbanks fails to teach or suggest the limitations of determining a work load
level associated with a processor as required by claims 33 and 44 (App. Br.
12).
We disagree with the Appellants’ contentions. We find Fairbanks
teaches that the power supply (consumption) and the clock frequency are
changed according to determining which mode (word processing or
numerical computing) the computer runs on (FF 4). The Fairbanks reference
teaches utilizing lower clock frequency and lower power supply for low
processing load such as word processing while ramping up the higher clock
frequency as well as higher power for higher processing load such as
numerical processing (FF 4). Thus, we conclude that Fairbanks discloses all
the limitations in claims 33 and 44.
Accordingly, we sustain the Examiner’s anticipation rejection of
claims 33 and 44. We further sustain the Examiner’s anticipation rejection
of dependent claims 42, and 43, which have not been separately argued,
and these claims therefore fall with their base claims. 37 C.F.R. § 41.37
(c)(1)(vii). See Nielson, 816 F.2d at 1572.

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35 U.S.C. § 103(a) Rejections
ISSUE 4
With respect to claim 34, the Appellants contend that neither Sheets
nor Fairbanks teaches or fairly suggests that “an amount of said increasing
power consumption is proportional to the increase of said work load
level”, required by claim 36 (App. Br. 15-16).
We disagree with the Appellants’ contention. We find Sheet teaches
that the power consumption is directly proportional to the operating clock
frequency (FF 1), and the clock frequency of a CPU is increasing from 500
kilohertz to 10 megahertz when the work load level from the sleep state
changes to the wakeup state (FF 3). We also find Fairbanks teaches that
when the work load level increases from word processing to numerical data
computation, the power consumption increases from 3 volts to 5 volts, which
is proportionally changing the power consumption (FF 4).
Accordingly, we sustain the Examiner’s obviousness rejection of
claim 34. We further sustain the Examiner’s obviousness rejection of
dependent claim 35, which has not been separately argued, and the claim
therefore falls with its base claim. 37 C.F.R. § 41.37 (c)(1)(vii). See In re
Nielson, 816 F.2d at 1572.
With respect to claims 36-37, the Appellants contend that the
Examiner has not identified any teaching within the cited references for the
teachings in claims 36-37 (App. Br. 16-17).
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Claim 37 recites “said increasing power consumption continues until
one of: a) no increase in work load level is detected over a previous
determination of work load level; and b) said processor has reached its
maximum power consumption level” (App. Br. Claims Appendix 3). The
body of claim 36 is the same as the step A of claim 37 (App. Br. Claims
Appendix 3).
First, we note that only one of the two limitations (a) and (b) need be
found in the prior art teachings to meet the claim. Furthermore, we find
Sheets teaches that the lowest power consumption corresponding the lowest
frequency (FF 1) is reached when the CPU/operating system is in sleep state
operated at 500 kilohertz, and the consumption level increases until CPU is
in wakeup state, the operating frequency is 10 megahertz (FF 3). In our
view, Sheets’ teaching the process that the operating clock frequency
changes from the sleep state (lower power consumption level) to the wake-
up state (higher power consumption level) reads on the claimed language of
claim 37. This increase of the power consumption continues while the clock
frequency is raised from 500 kilohertz until no increase in work load level is
detected over a predetermined work load level (the wakeup state is
detected/reached). Since the step A contains the same language as that of
claim 36, as discussed above, we conclude that Sheets teaches the limitation
of claims 36-37. In addition, we find Fairbanks teaches that the maximum
power consumption level (5 volts) is reached when the numerical data
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computation mode that the clock speed is maximum speed (FF 4). Thus, we
conclude that Fairbanks teaches step B of claim 37.
Accordingly, we sustain the Examiner’s obviousness rejection of
claims 36-37.
With respect to claims 38-41, we further sustain the Examiner’s
obviousness rejection of dependent claims 38-41, which has not been
separately argued, and these claims therefore fall with their base claims.
37 C.F.R. § 41.37 (c)(1)(vii). See Nielson, 816 F.2d at 1572.

VI. CONCLUSION
Based on our consideration of the totality of the record before us,
having weighed the evidence of obviousness found in the teachings of the
applied references with the Appellants’ countervailing evidence and
arguments for anticipation and nonobviousness, we conclude that the
claimed invention encompassed by appealed claims 22-33 and 42-44 would
have been unpatentable under 35 U.S.C. § 102, and claims 34-41 would
have been unpatentable as a matter of law under 35 U.S.C. § 103(a).
We also conclude that the Examiner has not erred in rejecting
claims 22-44 under nonstatutory obviousness-type double patenting
over claims 22-44 of copending Application No. 11/123,440 (now
claims 1-23 of US 7,392,416 B2), and provisional obviousness-type
double patenting over claims 24-47 of copending Application No.
11/137,037.
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VII. ORDER
We affirm the anticipation rejections of claims 22-33 and 42-44 under
35 U.S.C. § 102.
We affirm the obviousness rejection of claims 34-41 under 35 U.S.C.
§ 103(a).
We also affirm the provisional nonstatutory obviousness-type double
patenting rejections of claims 22-44.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136 (a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED

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