Ex Parte Ware et alDownload PDFPatent Trial and Appeal BoardNov 15, 201713143760 (P.T.A.B. Nov. 15, 2017) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/143,760 07/08/2011 Frederick A. Ware RBS2.P152US 8866 44429 7590 Peninsula Patent Group 5061 Crail Way El Dorado Hills, CA 95762 EXAMINER RANKIN, CANDICE A ART UNIT PAPER NUMBER 2132 NOTIFICATION DATE DELIVERY MODE 11/17/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): lkreisman@peninsulaiplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte FREDERICK A. WARE and HOLDEN JESSUP Appeal 2017-002317 Application 13/143,7601 Technology Center 2100 Before IRVIN E. BRANCH, NABEEL U. KHAN, and SHARON FENICK, Administrative Patent Judges. KHAN, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from the Non-Final Rejection of claims 1, 3—18, and 20-43. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 Appellants identify Rambus, Inc. as the real party in interest. App. Br. 3. Appeal 2017-002317 Application 13/143,760 STATEMENT OF THE CASE The Invention Appellants’ invention generally relates to “systems, methods and circuits for communicating between a memory controller and one or more memory devices.” Spec. | 1. Exemplary independent claim 1 is reproduced below. 1. A method for controlling a non-volatile integrated circuit memory device by a memory controller, the method comprising: sending a memory-access request from the memory controller to the non-volatile integrated circuit memory device, wherein the memory-access request is a read command or a write command to access storage cells during an access time interval, the read command specifying a read data transfer operation, and the write command specifying a write data transfer operation; after sending the memory-access request, sending to the non-volatile integrated circuit memory device a command that specifies performing a timing-calibration operation for the data transfer operation associated with the memory-access request, the timing-calibration operation to calibrate a timing of data relative to a timing reference; performing the data transfer operation for the memory- access request; and wherein the timing-calibration operation is completed during the access time interval. References and Rejections 1. Claims 1, 3-14, 16, 18, 20-29, 31, 33, 34, 36-38, and4(M3 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Bartley (US 2008/0028123 Al, pub. Jan. 31, 2008), Ware (US 2004/0054845 Al, pub. 2 Appeal 2017-002317 Application 13/143,760 Mar. 18, 2004), andDolev (US 8,046,541 Bl, issued Oct. 25, 2011). Non-Final Act. 5—12. 2. Claims 15 and 30 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Bartley, Ware, Dolev, and Shi (US 2007/0252735 Al, pub. Nov. 1,2007). Non-Final Act. 13—14. 3. Claims 17, 32, 35, and 39 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Bartley, Ware, Dolev, and Vorenkamp (US 2007/0170909 Al, pub. July 26, 2007). Non-Final Act. 1^U15. ANALYSIS Claim 1 Claim 1 recites “sending ... a command that specifies performing a timing-calibration operation . . . wherein the timing-calibration operation is completed during the access time interval.” The Examiner finds Bartley teaches or suggests this limitation by disclosing that timing signals are sent on a timing signal bus chain during a read/write operation. Ans. 2 (citing Bartley 11 176-182, Fig. 14). Appellants argue: [Njothing in the quoted passages relates to a “timing calibration,” especially as that term is understood by those having ordinary skill in the art, and in light of Applicant’s specification. Rather than relating to calibration, the references to “timing” pertain to signals such as clock signals that are sent by the controller to clock-in certain data signals at the memory devices. Applicant submits that the quoted passages fail to read on the claimed feature “wherein the timing-calibration operation is completed during the access time interval.” Reply Br. 5—6. We are unpersuaded by Appellants’ argument. Step 704, depicted in Figure 14 of Bartley, indicates the start of a read or write request. In step 3 Appeal 2017-002317 Application 13/143,760 708, which the Examiner finds teaches a timing-calibration operation, “the memory controller transmits timing signals to a chain of timing signals [if the memory chips are not self timed]. The timing signals are used by the memory chips to time accesses to arrays on the memory chips.” Bartley 1178; Figure 14. Steps 710 through 718 involve the transmission of the address/command word and the production and transmission of data. Id. ]ff[ 179-182; Figure 14. Step 720 indicates the end of the read or write request. Id. 1182; Figure 14. Thus, step 708 occurs after the start of the read/write request and before the end of the read/write request and is thus completed during the access time interval. Appellants do not present sufficient persuasive evidence or reasoning rebutting the Examiner’s finding that Bartley’s timing signals teach or suggest the claimed “timing-calibration operation” completed during the access time interval. Appellants do not present evidence distinguishing Bartley’s timing signals from the claimed timing calibration, either by way of extrinsic evidence or by pointing to portions of their Specification in support. Attorney “argument. . . cannot take the place of evidence.” In re Pearson, 494 F.2d 1399, 1405 (CCPA 1974). See, e.g., In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997) (attorney arguments or conclusory statements are insufficient to rebut a prima facie case). Accordingly, we sustain the Examiner’s rejection of claim 1. We also sustain the Examiner’s rejection of claims 3—18 and 20-43, which were argued together with claim 1 as a group. DECISION The Examiner’s rejection of claims 1, 3—18, and 20-43 is affirmed. 4 Appeal 2017-002317 Application 13/143,760 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 41.50(f). AFFIRMED 5 Copy with citationCopy as parenthetical citation