Ex Parte Wang et al

Patent Trial and Appeal Board

Sep 26, 2016

13113376 (P.T.A.B. Sep. 26, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/113,376 05/23/2011
127226 7590 09/28/2016
Birch, Stewart, Kolasch & Birch, LLP
P.O. Box 747
Falls Church, VA 22040-0747
FIRST NAMED INVENTOR
Chi-Lung WANG
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
6024-0ll6PUS1 9540
EXAMINER
FAYE-JOYNER, HANNAH A
ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
09/28/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
mailroom@bskb.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CHI-LUNG WANG, CHIA-HSIN CHEN,
and CHIEN-CHENG LIN
Appeal2015-005728
Application 13/113,376
Technology Center 2100
Before THU A. DANG, KRISTEN L. DROESCH, and
SCOTT B. HOWARD, Administrative Patent Judges.
HOW ARD, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Non-Final
Rejection of claims 1, 3-24, and 31-36, which constitute all of the claims
pending in this application. Claims 2 and 25-30 have been cancelled. Br.
25, 31. Although the action appealed from is a non-final rejection, because
the application has been twice rejected we have jurisdiction pursuant to 35
U.S.C. §§ 6 and 134. Ex parte Lemoine, 46 USPQ2d 1420, 1423 (BPAI
1994) (precedential).
We reverse.
1 Appellants identify Silicon Motion, Inc. as the real party in interest. Br. 1.
Appeal2015-005728
Application 13/113,376
THE INVENTION
The disclosed and claimed invention is directed to an apparatus for
managing and accessing flash memory module. Abstract.
Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. A controller for managing a flash memory module,
compnsmg:
a communication interface for coupling with a host device;
and
a processing circuit coupled with the communication
interface and configured for:
writing a plurality of data and associated logical
addresses into multiple physical pages of multiple data
blocks,
recording a first address group in a first page of a
first addressing block in an order based on an address
order of a first set of M sequential logical addresses,
wherein the first address group comprises multiple
addresses of a first set of M physical pages of the multiple
data blocks, and the first set of 1\1 physical pages
corresponds to the first set of M sequential logical
addresses,
recording a second address group in a second page
of the first addressing block in an order based on an
address order of a second set of M sequential logical
addresses, wherein the second address group comprises
multiple addresses of a second set of M physical pages of
the multiple data blocks, and the second set ofM physical
pages corresponds to the second set of M sequential
logical addresses,
recording a third address group in a first page of a
second addressing block in an order based on an address
order of a third set of M sequential logical addresses,
wherein the third address group comprises multiple
addresses of a third set ofM physical pages of the multiple
data blocks, and the third set of M physical pages
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Appeal2015-005728
Application 13/113,376
corresponds to the third set of M sequential logical
addresses, and
recording a fourth address group in a second page
of the second addressing block in an order based on an
address order of a fourth set of M sequential logical
addresses, wherein the fourth address group comprises
multiple addresses of a fourth set of M physical pages of
the multiple data blocks, and the fourth set of M physical
pages corresponds to the fourth set ofM sequential logical
addresses;
wherein M is an integer larger than one, the second set of
M logical addresses is successive to the first set of M logical
addresses, the third set ofM logical addresses is successive to the
second set ofM logical addresses, and the fourth set ofM logical
addresses is successive to the third set of M logical addresses,
wherein the multiple data blocks, the first addressing
block, and the second addressing block are different, and
wherein the physical pages of the data blocks and the
physical pages of the addressing blocks are separate.
REFERENCES
The prior art relied upon by the Examiner as evidence in rejecting the
claims on appeal is:
Doi us 5,257,361 Oct. 26, 1993
Plamondon US 2008/0229025 Al Sept. 18, 2008
Chang US 7 ,526,599 B2 Apr. 28, 2009
Yano US 2010/0312948 Al Dec. 9, 2010
REJECTIONS
Claims 1, 3---6, 8, 10-14, 19, 20, 22-24, 31, 33, 34, and 36 stand
rejected under pre-AIA 35 U.S.C. § 102(b) as being anticipated by Chang.
Non-Final Act. 2-11.
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Appeal2015-005728
Application 13/113,376
Claims 7, 15, 21, and 32 stand rejected under pre-AIA 35 U.S.C.
§ 103(a) as being unpatentable over Chang in view of Doi. Non-Final Act.
11-12.
Claims 9 and 35 stand rejected under pre-AIA 35 U.S.C. § 103(a) as
being unpatentable over Chang in view ofYano. Non-Final Act. 13.
Claims 16-18 stand rejected under pre-AIA 35 U.S.C. § 103(a) as
being unpatentable over Chang in view of Doi and Plamondon. Non-Final
Act. 13-16.
ANALYSIS
We have reviewed the Examiner's rejection in light of Appellants'
arguments that the Examiner erred. In reaching this decision, we have
considered all evidence presented and all arguments made by Appellants.
We are persuaded by Appellants' arguments regarding the pending claims.
Appellants argue the Examiner erred in finding Chang discloses a
processor that performs the "writing" and "recording" limitations recited in
claim 1. Br. 15-19. According to Appellants, Chang does not disclose
writing content on a single page of an addressing block that corresponds to
multiple physical pages of multiple data blocks as recited in claim 1. Br. 18.
More particularly, Appellants argue "the content stored in a single physical
page of a physical block of Chang only corresponds to a single logical
page." Br. 18 (citing Chang 3:16-34); see also Br. 19 ("In fact, Chang in
col. 9, Lines 30-31 and col. 9, line 65 to col. 10 line 4 discloses that a single
logical group includes multiple pages, and the content of a single logical
group is stored in multiple pages of a physical group, NOT stored in a single
physical page of a physical group.").
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Application 13/113,376
The Examiner finds Chang discloses the writing and recording
limitations at column 3, lines 16-34. Non-Final Act. 3-5. The Examiner
also concludes the claim language was not clear. Ans. 4.
We are persuaded by Appellants' arguments as the Examiner has not
identified sufficient evidence or provided sufficient explanation as to how
Chang discloses the disputed limitations as recited in claim 1. Although
Chang discloses storing content in a physical page of a physical group of a
data block, the cited section of Chang does not disclose recording multiple
addresses on a single physical page as recited in claim 1.
Because we agree with at least one of the dispositive arguments
advanced by Appellants, we need not reach the merits of Appellants' other
arguments.
Accordingly, we are constrained on this record to reverse the
Examiner's rejection of claim 1, along with the rejections of claim 31, which
recite limitations commensurate in scope to the disputed limitations
discussed above, and dependent claims 3-24 and 32-36.
DECISION
For the above reasons, we reverse the Examiner's decisions rejecting
claims 1, 3-24, and 31-36.
REVERSED
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