Ex parte Wang

Board of Patent Appeals and Interferences

May 12, 2000

08294235 (B.P.A.I. May. 12, 2000)

Application for patent filed August 22, 1994, entitled1
"Artificial Neuron And Method Of Using Same," which is a
continuation of Application 08/076,602, filed June 14, 1993,
now U.S. Patent 5,390,136, issued February 14, 1995.
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THIS OPINION WAS NOT WRITTEN FOR PUBLICATION
The opinion in support of the decision being entered
today (1) was not written for publication in a law
journal and (2) is not binding precedent of the Board.
_______________
Paper No. 22
UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES

Ex parte SHAY-PING T. WANG

Appeal No. 1997-3793
Application 08/294,2351

ON BRIEF

Before THOMAS, BARRETT, and BLANKENSHIP, Administrative Patent
Judges.
BARRETT, Administrative Patent Judge.
DECISION ON APPEAL
Appeal No. 1997-3793
Application 08/294,235
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This is a decision on appeal under 35 U.S.C. § 134 from
the final rejection of claims 1-4 and 12-15. Claims 1, 3, 12,
and 14 were amended (part of Paper No. 18) in response to a
new ground of rejection in the Examiner's Answer and the new
rejection was withdrawn (Supplemental Examiner's Answer, Paper
No. 19).
We reverse.
BACKGROUND
The disclosed invention is directed to a neuron circuit
and method of producing a neuron output which multiplies
together a plurality of gated input signals x and aigi
predetermined weight, where at least one g is greater thani
one.
Claim 1, as amended by the amendment filed July 18, 1997,
(part of Paper No. 18) is reproduced below.
1. A neuron circuit comprising:
a multiplier circuit in communication with a
plurality of gated input signals, each of said gated
input signals representing one of a plurality of inputs
to said neuron circuit raised to an exponential power of
one of a plurality of gating functions g , said multiplieri
circuit for multiplying said gated input signals together
to produce a product and for multiplying said product by
Appeal No. 1997-3793
Application 08/294,235
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a predetermined weight to generate without a threshold
comparison a neuron output signal;
wherein at least one of said plurality of gating
functions g is greater than 1.i
The Examiner relies on the following prior art:
Hata et al. (Hata), Gate Model Networks for Minimization
of Multiple-Valued Logic Functions, Proceedings of the
Twenty-Third International Symposium on Multiple-Valued
Logic, IEEE, 24-27 May, 1993, pp. 29-34.
Claims 1-4 and 12-15 stand rejected under 35 U.S.C.
§ 102(a) as being clearly anticipated by Hata.
We refer to the Final Rejection (Paper No. 10) (pages
referred to as "FR__") and the Examiner's Answer (Paper
No. 17) (pages referred to as "EA__") for a statement of the
Examiner's position and to the Appeal Brief (Paper No. 16)
(pages referred to as "Br__") and the Reply Brief (Paper
No. 18) (pages referred to as "RBr__") for a statement of
Appellant's arguments thereagainst.
OPINION
The claims are grouped to stand or fall together.
Claim 1 is taken as representative.
Appeal No. 1997-3793
Application 08/294,235
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Appellant argues that Hata does not disclose an input
signal raised to an exponential power of one of the gating
functions g , wherein the gating function g is greater than 1. i i
These limitations are found in all the independent claims.
The Examiner finds (FR2) that Hata discloses an input
raised to a power at page 32, section 4, line 5 ("1. literal:
x ..."), and equations (13) and (14). The Examiner furtherS
finds (EA7) that "x " at page 33, second column, line 14,12
shows x raised to the power of 2.1
Appellant responds that the notation in Hata, while using
superscripts which could be easily confused with
exponentiation, has nothing to do with exponentiation (Br3-5;
RBr2-3).
Appellant is clearly correct. The term x is called aij
"literal" of input variable x, where a literal is a
propositional variable or its negation. For an r-valued
n-variable function F(X), X={x ,x ,...,x } is the set of1 2 n
n-variables, where x takes on values from R={0,1,...,r-1}i
(page 32, section 4). The term x refers to input variable xi ij
having the value j from the r values of set R, not x to thei
jth power. Since each input x can have one of r values,i
Appeal No. 1997-3793
Application 08/294,235
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there are n·r inputs to each node in the hidden layer. Thus,
in Example 3 on page 33, for a 2-variable (X={x , x }) 4-valued1 2
(R={0,1,2,3}) function there are 2·4=8 inputs
(x ,x ,x ,x ,x ,x ,x ,x ). In the term x , x refers to the1 1 1 1 2 2 2 2 1 10 1 2 3 0 1 2 3 2
first variable and the superscript 2 refers to the value 2,
not a power. Because Hata does not disclose raising an input
to a power greater than one, the anticipation rejection of
claims 1-4 and 12-15 is reversed.
Although Appellant has elected to only argue the
exponential power limitation, we also note that Hata does not
disclose a multiplier circuit for multiplying the gated input
signals together. In equation (13), the dots between the
terms refer to a logical AND operation (page 30, right column,
line 5), not a product. Figure 1 shows a summer as evidenced
by equation (2). For this additional reason, the anticipation
rejection of claims 1-4 and 12-15 is reversed.
REVERSED
Appeal No. 1997-3793
Application 08/294,235
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JAMES D. THOMAS )
Administrative Patent Judge )
)
)
)
) BOARD OF PATENT
LEE E. BARRETT ) APPEALS
Administrative Patent Judge ) AND
) INTERFERENCES
)
)
)
HOWARD B. BLANKENSHIP )
Administrative Patent Judge )
Appeal No. 1997-3793
Application 08/294,235
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Anthony J. Sarli, Jr.
MOTOROLA, INC.
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