Ex Parte Wang

Patent Trial and Appeal Board

Aug 31, 2017

12760240 (P.T.A.B. Aug. 31, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/760,240 04/14/2010 Feng Wang QC091984 8661
12371 7590 09/05/2017
Mnnrv rre.issle.r Olrk & T owe P P /OT TAT POMM EXAMINER
4000 Legato Road, Suite 310
Fairfax, VA 22033
HUYNH, KIM T
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
09/05/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
meo.docket@mg-ip.com
meo@mg-ip.com
ocpat_uspto@qualcomm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte FENG WANG
Appeal 2015-005689
Application 12/760,240
Technology Center 2100
Before ERIC S. FRAHM, JUSTIN BUSCH, and
JAMES W. DEJMEK, Administrative Patent Judges.
BUSCH, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the rejection
of claims 1—23. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Appeal 2015-005689
Application 12/760,240
CLAIMED SUBJECT MATTER
Claims 1,7, 13, 18, and 23 are independent claims. The claims relate
generally to bus arbitration and, more specifically, to managing memory
requests in a shared memory system in a manner that reduces memory
access power. Spec. 12. Claim 1 is reproduced below:
1. A method of arbitrating requests from bus masters for
access to shared memory in a processing system
comprising:
dividing the shared memory into memory channels;
determining power modes associated with the
memory channels;
assigning priorities to the requests based at least in
part on the power modes; and
scheduling the requests based on the assigned
priorities.
REJECTION
Claims 1—23 stand rejected under 35 U.S.C. § 103(a) as unpatentable
in view of Cho (US 2009/0063791 Al; Mar. 5, 2009) and Hur (US
2009/0016137 Al; Jan. 15, 2009). Final Act. 2-5.
OPINION
The Examiner finds Cho discloses the dividing and determining
limitations and Hur discloses the assigning and scheduling steps recited in
independent claim 1 and commensurately recited in independent claims 7,
13, 18, and 23.1 Final Act. 2—3. The Examiner provides a reason a person
having ordinary skill in the art would have combined the cited disclosures of
Cho and Hur. Id. The Examiner also finds Cho teaches each of the
1 System claim 7 does not recite an element configured to perform the
scheduling step.
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Application 12/760,240
additional limitations recited in dependent claims 2—6, 8—12, 14—17, and 19-
22. Id. at 3—A.
Appellant argues Cho does not teach a shared memory, dividing the
shared memory into channels, or determining power modes of the memory
channels and Hur does not teach assigning priorities to the requests based on
the determined power modes, as recited in each of the independent claims.
App. Br. 7—16; Reply Br. 2—\. Appellant also contends Cho does not even
discuss memory pages, let alone teach or suggest assigning priorities based
on maximizing page hit rate, as recited in dependent claims 5, 11, 17, and
22. App. Br. 16—17; Reply Br. 4. However, because it is dispositive of this
Appeal, we address only Appellant’s assertion that Cho fails to teach or
suggest a shared memory.
We start by construing a shared memory, which is central to
Appellant’s argument. The plain meaning of a “shared memory” is a
“portion of memory used by parallel-processor computer systems to
exchange information.” Microsoft Computer Dictionary 600 (5th ed.
2002). Such a definition is consistent with Appellant’s Specification. Spec.
13 (“A shared or global memory space may be accessed by multiple
processors or processing elements through a bus or interconnect system.”).
The Examiner makes no findings and points to no evidence regarding a
proper construction of a “shared memory,” but finds Cho teaches a shared
memory for the reasons discussed below. Accordingly, based on the
evidence before us, we construe a shared memory as a memory that is
accessed by more than one processor.
A proper obviousness analysis includes identifying the scope and
content of the prior art and ascertaining the difference between the prior art
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Appeal 2015-005689
Application 12/760,240
and the claims being analyzed. Graham v. John Deere Co., 383 U.S. 1, 17
(1966). Appellant acknowledges that shared memories, as well as dividing
shared memories into memory channels, are well-known in the art. Spec.
113-10. For example, Appellant’s Specification states that “[sjystem
architectures with shared memory structures are well known in the art.” Id.
13. Read and write requests to access the shared memory “are serviced by
‘memory controllers.’” Id. The Specification further states that “shared
memory space is typically interleaved,” which means the “memory system
comprises two or more memory channels.” Id. 14. “Memory data is
distributed among the memory channels such that data words in different
memory channels may be accessed in parallel.” Id. The Specification also
acknowledges that various schemes for prioritizing memory access requests
as well as techniques to maintain memory channels in powered down states
in order to conserve power are well-known. Id. 5—9.
One example of a known technique for powering down memory
channels (although not in a shared memory) is disclosed by Cho. Cho
Abstract, Fig. 1,147. Similar to Appellant’s Specification, Cho discloses
accessing each of its memory channels in parallel. Cho Tflf 42-44; Spec. 14.
Hur discloses one known scheme for prioritizing memory access requests
that includes managing whether particular portions (i.e., ranks) of its
memory are powered or powered down. Hur Abstract, Figs. 2—6, 15, 16,
34, 39, 40.
Initially, we note that some of Appellant’s arguments seem to
mischaracterize either Cho’s disclosure or the scope of what is required by
Appellant’s claims. In particular, Appellant contends Cho discloses two
separate memories, not a single shared memory. App. Br. 7—8. However,
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Appeal 2015-005689
Application 12/760,240
Clio’s memory channels appear to be equivalent to Appellant’s disclosed
and claimed memory channels. Specifically, Cho discloses that its graphic
core accesses its graphic memory, which is divided into two (or more)
graphic memory channels, through controllers each associated with a
respective memory channel. Cho 39-42. Similarly, Appellant’s
Specification depicts and describes a similar arrangement. See Spec. ]Hf 25,
26, Figs. 1, 2. Thus, we agree with the Examiner that paragraphs 39 through
41, and specifically memory channels 0 and 1, suggest dividing a memory
into memory channels. See Final Act. 2.
Nevertheless, we ultimately agree with Appellant that Cho fails to
teach or suggest dividing a shared memory into memory channels because
Cho fails to suggest a shared memory, as further discussed below.
The Examiner finds paragraph 19 of Cho indicates its two memory
controllers provide an interface between its two memory channels “and the
data processor wherein the data processor is shared memory between first
and second channels memories[, which] is equivalent [to Appellant’s]
recited claims.” Final Act. 5; Ans. 5. The Examiner finds Cho’s disclosure
of accessing multiple memory channels in parallel supports a finding that
Cho teaches a shared memory. Ans. 5.
The Examiner also finds Cho’s memory controllers (Fig. 1, items
1041.0 and 1041.1) can each communicate with each of the graphic memory
channels (Fig. 1, items 103.0 and 103.1). Id. Finally, the Examiner finds
Cho’s graphic core “processes graphics data according to a command from
the system OS/BIOS” and reads data from and writes data to multiple
graphic memory channels to process the graphics data, which “means that
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Application 12/760,240
the data processor is sharing memory with other devices [and] other devices
can also access the graphic memory as well.” Id.
Appellant argues “Cho is entirely silent with regard to a ‘shared’
memory,” and is therefore incapable of teaching or suggesting managing
requests for access to a shared memory or dividing a shared memory into
memory channels. See App. Br. 8—9 (emphasis omitted). Appellant also
contends the Examiner’s finding that Cho’s “data processor is shared
memory between first and second channels memories,” Final Act. 5, is
illogical because a processor does not teach or suggest a “shared memory”
under any reasonable construction of the term. App. Br. 9. Finally,
Appellant asserts the Examiner’s findings that other devices access the
graphics memory is merely speculation and unsupported by Cho. Reply
Br. 2.
We agree with the Examiner that Cho’s graphic core, which is also
referred to as a data processor, may send access requests to the graphic
memory channels in parallel via the memory controllers. As discussed
above, however, Cho’s memory channels are equivalent to Appellant’s
claimed memory channels, which also may be accessed in parallel. See
Spec. 14. However, parallel access of memory channels is a result of
having a memory controller for each channel and is unrelated to whether the
memory divided into those channels is a shared memory, as recited in
Appellant’s claims. See id. ^fl[ 4—6; Cho ^fl[ 42, 44.
Additionally, the Examiner’s finding that Cho’s graphic core teaches
or suggests the recited shared memory is inconsistent with the finding that
Cho’s graphic memory channels teach or suggest the recited memory
channels because Cho’s graphic memory channels are separate and distinct
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Application 12/760,240
from its graphic core. Here, the Examiner has not provided sufficient
persuasive reasoning or explanation to support the finding that Cho teaches
or suggests dividing the graphic core into the memory channels. Thus, we
agree with Appellant that Cho’s data processor does not teach or suggest the
recited shared memory.
Furthermore, we agree with Appellant that Cho does not teach or
suggest any processor other than its graphic core accessing its memory
channels. Cho, of course, is not limited to the specific embodiment depicted
in Figure 1. However, the Examiner has not pointed to anything in Cho to
suggest that multiple processors would access Cho’s memory channels. In
fact, Cho’s background explains describes a system in which the invention
could be employed as having a “main memory to read and write data
processed by a main processor controlling the computer system (such as a
central processing unit (CPU)), and a graphic memory to read and write
graphic data processed by a graphic processor.” Cho 1 5.
Therefore, the Examiner’s finding that Cho teaches other devices
accessing Cho’s graphic memory channels is not supported by substantial
evidence. Although Appellant acknowledges that shared memories divided
into memory channels, prioritizing and scheduling access requests to shared
memory channels, and power management of memory channels are well-
known, the Examiner’s conclusion of obviousness rests on a finding that
Cho discloses a shared memory. Given our construction of shared memory
and determinations discussed above, it follows that we determine the
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Application 12/760,240
Examiner erred in finding that Cho teaches or suggests the recited “shared
memory.”2
As mentioned above, each of the independent claims recites a shared
memory and, therefore, each dependent claim also recites a shared memory
via its dependency from one of the independent claims. Accordingly,
constrained by this record, we cannot sustain the Examiner’s rejection of
claims 1—23.
DECISION
For the reasons discussed above, we reverse the Examiner’s decision
to reject claims 1—23.
REVERSED
2 While the Board is authorized to reject claims under 37 C.F.R. § 41.50(b),
no inference should be drawn when the Board elects not to do so. See
Manual of Patent Examining Procedure (MPEP) § 1213.02.
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