Ex Parte Wan et al

Board of Patent Appeals and Interferences

Dec 13, 2011

10642318 (B.P.A.I. Dec. 13, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________
Ex parte WADE KEITH WAN and SHERMAN (XUEMIN) CHEN
____________
Appeal 2009-010933
Application 10/642,3181
Technology Center 2400
____________

Before JEAN R. HOMERE, JAY P. LUCAS, and
MICHAEL R. ZECHER, Administrative Patent Judges.

ZECHER, Administrative Patent Judge.

DECISION ON APPEAL

1 Filed on August 15, 2003. The real party in interest is Broadcom Corp.
(App. Br. 2.)
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I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) (2002) from the
Examiner’s Final Rejection of claims 1-22. (App. Br. 2.)2 Responsive to a
restriction requirement, claims 23 and 24 have been withdrawn from
consideration. (Id.) We have jurisdiction under 35 U.S.C. § 6(b) (2008).
We affirm-in-part.
Appellants’ Invention
Appellants invented a method for generating pseudo-random numbers
that are used as encryption keys or seed values in cryptographic applications.
(Spec. ¶ [10].) According to Appellants, the claimed invention implements a
pseudo-random number generator using one or more linear feedback shift
registers (hereinafter “LFSRs”) that employ a number of techniques to
conceal the behavior of its internal parameters. (Id.)
Illustrative Claims
1. A method of generating pseudo-random numbers
using a linear feedback shift register in which the correlation
between successive pseudo-random numbers is reduced, said
method comprising sampling output sequences of said linear
feedback shift register with a specified periodicity.

7. A method of generating pseudo-random numbers
using linear feedback shift registers in which the correlation
between successive pseudo-random numbers is reduced, said
method comprising periodically switching between iterative
outputs generated by at least a first linear feedback shift register
and iterative outputs generated by at least a second linear
feedback shift register.

2 All references to the Appeal Brief are to the Appeal Brief filed September
24, 2008, which replaced the Appeal Brief filed on June 23, 2008.
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11. A method of encrypting a pseudo-random number
generated by a linear feedback shift register comprising
operating a nonlinear operator on said pseudo-random number
and one or more operands.

17. A method of further encrypting a pseudo-random
number generated from a linear feedback shift register by using
a hashing function comprising:
receiving said pseudo-random number generated from
said linear feedback shift register; and
varying the initial value of said hashing function over
time by way of a function operating on one or more variables.

Prior Art Relied Upon
Furuta US 5,327,522 July 5, 1994
Thomas US 2003/0072059 A1 Apr. 17, 2003
Gressel US 2004/0205095 A1 Oct. 14, 2004
(filed Apr. 14, 2003)
Walmsley US 2005/0066168 A1 Mar. 24, 2005
(effectively filed July 10, 1998)
Meiyappan US 6,993,542 B1 Jan. 31, 2006
(filed Mar. 12, 2001)

Rejections on Appeal
Claims 1-6, 14-16, and 20-22 stand rejected under 35 U.S.C. § 102(e)
as being anticipated by Gressel. (Ans. 3-4.)
Claim 1 stands rejected under 35 U.S.C. § 102(e) as being anticipated
by Meiyappan. (Ans. 6.)
Claims 7-10 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Furuta. (Ans. 4-5.)
Claims 11-13 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Thomas. (Ans. 5-6.)
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Claim 17 stands rejected under 35 U.S.C. § 102(e) as being
anticipated by Walmsley. (Ans. 6.)
Claims 18 and 19 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Furuta and Gressel. (Ans. 7.)3
Appellants’ Contentions
1. Appellants contend that since Gressel discloses that sampling is
typically enacted only randomly and preferably not more often than once in
64 system clock cycles, Gressel does not describe “sampling output
sequences of said linear feedback shift register with a specified periodicity,”
as recited in independent claim 1. (Reply Br. 6-8.)
2. Appellants contend that the textual portions of Meiyappan
relied upon by the Examiner, namely the Abstract and column 1, lines 19-24,
do not describe reducing the correlation between successive pseudo-random
numbers, as required by the preamble of independent claim 1. (App. Br. 14-
16.) Appellants also argue that Meiyappan’s disclosure of inputting the
output of an LFSR into a sampling switch, which in turn samples during
periods when its sampling input line is active and does not sample when its
sampling input line is inactive, does not describe “sampling output

3 The Examiner appears to have rejected dependent claim 19 under 35
U.S.C. § 102(e) as being anticipated by Furuta. (Fin. Rej. 5-6; Ans. 4-5.)
However, we note that dependent claim 18, from which claim 19 depends,
stands rejected under 35 U.S.C. § 103(a) as being unpatentable over the
combination of Furuta and Gressel. (Fin. Rej. 8; Ans. 7.) Therefore, since
Gressel is part of the rejection of dependent claim 18, we will treat
dependent claim 19 as being rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Furuta and Gressel. Appellants failed
to separately argue this on appeal. Therefore, Appellants have waived any
such arguments. See In re Watts, 354 F.3d 1362, 1367 (Fed. Cir. 2004).
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sequences of said linear feedback shift register with a specified periodicity,”
as recited in independent claim 1. (App. Br. 16-17; Reply Br. 26.) Further,
Appellants allege that Meiyappan merely discloses periodically clocking the
output of the sampling switch and, therefore, does not describe sampling the
output sequence of an LFSR, as claimed. (App. Br. 17-18; Reply Br. 26-27.)
3. Appellants contend that since Furuta only discloses one LFSR
that comprises seven flip-flops, Furuta does not describe “a first linear
feedback shift register” and “a second linear feedback shift register,” as
recited in independent claim 7. (App. Br. 20; Reply Br. 29-32.)
4. Appellants contend that the textual portions of Thomas relied
upon by the Examiner, namely claim 29 and paragraphs [0155] and [0213],
do not describe “operating a nonlinear operator on said pseudo-random
number and one or more operands,” as recited in independent claim 11.
(App. Br. 24-27; Reply Br. 38-41.)
5. Appellants contend that the textual portions of Walmsley relied
upon by the Examiner, namely paragraphs [0358-0365] and [0942-0943], do
not describe “varying the initial value of said hashing function over time by
way of a function operating on one or more variables,” as recited in
independent claim 17. (App. Br. 27-30; Reply Br. 41-44.) In particular,
Appellants argue that Walmsley’s disclosure of an authentication chip that
performs validation of keys using an SHA-1 algorithm, wherein the results
of using the algorithm are compared against an internal checksum value,
does not describe the disputed claim limitation. (Reply Br. 47-48.)
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Examiner’s Findings and Conclusions
1. The Examiner finds that upon reviewing Appellants’
Specification for context, the claim term “specified periodicity” may be
interpreted as a period/interval time/clock cycle. (Ans. 8.) Further, the
Examiner finds that Gressel discloses an LFSR sampling randomly once in
64 system clock cycles. (Id.) Consequently, the Examiner finds that Gressel
describes “sampling output sequences of said linear feedback shift register
with a specified periodicity,” as recited in independent claim 1. (Id.)
2. The Examiner finds that Meiyappan’s disclosure of generating
truly random numbers using a random number generating technique, which
includes periodically clocking the output of a sampling switch, is similar to
using periodic sampling to reduce the correlation between successive outputs
of an LFSR. (Id. at 11.) Therefore, the Examiner finds that since
Meiyappan discloses an LFSR that uses periodic sampling, Meiyappan
describes reducing the correlation between successive outputs of an LFSR,
as required by the preamble of independent claim 1. (Id.) Further, the
Examiner finds that Meiyappan’s disclosure of a sampling switch that
samples the outputs of the LFSR, in conjunction with periodically clocking
the output of the sampling switch, describes “sampling output sequences of
said linear feedback shift register with a specified periodicity,” as recited in
independent claim 1. (Id. at 11-12.)
3. The Examiner finds that Furuta discloses a switching circuit
that switches between seven flip flops of a random number generator. (Id. at
12.) In particular, the Examiner finds that since the seven flip flops amount
to seven different LFSRs, Furuta describes using the switching circuit to
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switch between “a first linear feedback shift register” and “a second linear
feedback shift register,” as recited in independent claim 7. (Id. at 13.)
4. The Examiner finds that Thomas’ disclosure of operating a non-
linear shift register (i.e., operator) in order to generate non-linear filtered
output on a random number and one or more operands (i.e., first and second
taps) describes “operating a nonlinear operator on said pseudo-random
number and one or more operands,” as recited in independent claim 11. (Id.
at 14.)
5. The Examiner finds that Walmsley’s disclosure of a protocol
that applies a hash MMAC-SHA-1 amounts to running a hash algorithm on
the keys and comparing the result against an internal checksum value. (Id. at
15.) Consequently, the Examiner finds that Walmsley’s checksum register
is applying a hash function that operates on the keys and, therefore,
describes “varying the initial value of said hashing function over time by
way of a function operating on one or more variables,” as recited in
independent claim 17. (Id.)

II. ISSUES
1. Have Appellants shown that the Examiner erred in finding that
Gressel describes “sampling output sequences of said linear feedback shift
register with a specified periodicity,” as recited in independent claim 1.
2. Have Appellants shown that the Examiner erred in finding that
Meiyappan anticipates independent claim 1? In particular, the issue turns on
whether Meiyappan describes:
(a) “the correlation between successive pseudo-random numbers is
reduced,” as recited in the preamble of independent claim 1; and
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(b) “sampling output sequences of said linear feedback shift
register with a specified periodicity,” as recited in independent claim 1.
3. Have Appellants shown that the Examiner erred in finding that
Furuta describes “a first linear feedback shift register” and “a second linear
feedback shift register,” as recited in independent claim 7.
4. Have Appellants shown that the Examiner erred in finding that
Thomas describes “operating a nonlinear operator on said pseudo-random
number and one or more operands,” as recited in independent claim 11.
5. Have Appellants shown that the Examiner erred in finding that
Walmsley describes “varying the initial value of said hashing function over
time by way of a function operating on one or more variables,” as recited in
independent claim 17.

III. FINDINGS OF FACT
The following Findings of Fact (hereinafter “FF”) are shown by a
preponderance of the evidence.
Gressel
FF 1. Gressel discloses that LFSRs are linear in the sense that any
sequence in the register is followed by another defined sequence in the
register, cyclically, until all the sequences have been generated. (¶ [0044].)
FF 2. Gressel discloses configuring or modifying LFSRs with
feedback schemes. (¶ [0045].) According to Gressel, sampling is typically
enacted only randomly and preferably not more often than once in 64 system
clock cycles. (¶ [0049].)
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Meiyappan
FF 3. Meiyappan’s figure’s 1 illustrates a random number generation
system. (Col. 2, ll. 41-42.) In particular, Meiyappan discloses providing the
output of an LFSR (112) as a sampling input to a sampling switch (110).
(Col. 3, ll. 20-21.) Further, Meiyappan discloses periodically clocking the
output of the sampling switch (110) into a random storage register (114).
(Id. at ll. 29-32.)
Furuta
FF 4. Furuta’s figure 125 illustrates a random number generator
(331). (Col. 67, ll. 15-16.) In particular, Furuta discloses an LFSR (1302)
that includes flip flops (13021 through 13027), an exclusive-OR gate (1305),
and a switching circuit (1309). (Id. at ll. 33-35.)
Thomas
FF 5. Thomas’ figure 10 illustrates a submethod (905) for generating
non-linear filtered output bits from shift registers. (¶ [0155].) In step
(1005), Thomas discloses selecting a first tap, such as tap (735), and a
second tap, such as tap (740), of LFSR (705). (Id.)
FF 6. Thomas discloses generating a key stream from feedback taps
in a non-linear manner, which prevents any attacks on the communication
channel when the key stream is used to carry information between parties.
(¶ [0213].)
Walmsley
FF 7. Walmsley discloses a protocol that does not reveal the secret
keys during the authentication process. (¶ [0359-0360].) In particular,
Walmsley discloses encrypting the time varying random number such that it
is not revealed during the authentication process. (¶ [0360].)
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FF 8. Walmsley discloses running a SHA-1 algorithm on the keys and
comparing the results against an internal checksum value. (¶ [1330].)

IV. ANALYSIS
35 U.S.C. § 102(e) Rejection—Gressel
Claim 1
We find error in the Examiner’s anticipation rejection of independent
claim 1. Independent claim 1 recites, inter alia, “sampling output sequences
of said linear feedback shift register with a specified periodicity.”
First, we consider the scope and meaning of the claim term “a
specified periodicity,” which must be given the broadest reasonable
interpretation consistent with Appellants’ disclosure. As explained in In re
Morris, 127 F.3d 1048 (Fed. Cir. 1997):
[T]he PTO applies to the verbiage of the proposed claims the
broadest reasonable meaning of the words in their ordinary
usage as they would be understood by one of ordinary skill in
the art, taking into account whatever enlightenment by way of
definitions or otherwise that may be afforded by the written
description contained in the applicant's specification.
Id. at 1054. See also In re Zletz, 893 F.2d 319, 321 (Fed. Cir. 1989) (stating
that during examination “claims must be interpreted as broadly as their terms
reasonably allow”). Appellants’ Specification states that:
[t]here are advantages to sampling the LFSR output sequence
with periodicity equal to n=3.… Although Figure 3 provides an
embodiment of a 3 bit LFSR implementation in which outputs
are sampled every 3 iterations, it is contemplated that other
embodiments may be implemented using a n bit LFSR where
n≠3, in which the output sequence is sampled every n iterations.
It is further contemplated that other embodiments may be
implemented using an n bit LFSR, in which the output sequence
may be sampled with period L, for which L≠n.
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(Spec. ¶ [29].)
Upon reviewing Appellants’ Specification for context, we agree with
the Examiner that the claim term “a specified periodicity” may be broadly,
but reasonably construed as a specific period, interval of time, or number of
clock cycles. (Ans. 8.)
At best, we find that Gressel discloses sampling the output of a LFSR
only randomly and preferably not more often than once in 64 clock cycles.
(FFs 1 and 2.) Consequently, we agree with Appellants that Gressel does
not describe sampling the output of the LFSR within a specific period,
interval of time, or number of clock cycles (e.g., such as every 3 clock
cycles), but rather only randomly samples the output of the LFSR at period
which is preferably greater than or equal to 64 clock cycles. (Reply Br. 7-8.)
Therefore, we find that the Examiner improperly relied upon Gressel to
describe the disputed claim limitation. It follows that Appellants have
shown that the Examiner erred in finding that Gressel anticipates
independent claim 1.
Claims 2-6, 14-16, and 20-22
Since dependent claims 2-6, 14-16, and 20-22 incorporate by
reference the same claim limitation as independent claim 1, we find that
Appellants have also shown that the Examiner erred in finding that Gressel
anticipates these claims for the same reasons set forth in our discussion of
independent claim 1.
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35 U.S.C. § 102(e) Rejection—Meiyappan
Claim 1
We do not find error in the Examiner’s anticipation rejection of
independent claim 1. Independent claim 1 recites, inter alia, 1) “the
correlation between successive pseudo-random number is reduced[;]” and 2)
“sampling output sequences of said linear feedback shift register with a
specified periodicity.”
First, we are not persuaded by Appellants’ argument that Meiyappan
does not describe “the correlation between successive pseudo-random
numbers is reduced,” as recited in the preamble of independent claim 1.
(App. Br. 15-16; 22-25.) In general, a preamble is construed as a limitation
“if it recites essential structure or steps, or if it is ‘necessary to give life,
meaning, and vitality’ to the claim.” Catalina Mktg. Int'l, Inc. v.
Coolsavings.com, Inc., 289 F.3d 801, 808 (Fed. Cir. 2002) (quoting Pitney
Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305 (Fed. Cir. 1999)).
A preamble is not limiting, however, “‘where a patentee defines a
structurally complete invention in the claim body and uses the preamble only
to state a purpose or intended use for the invention.”’ Id. (quoting Rowe v.
Dror, 112 F.3d 473, 478 (Fed. Cir. 1997)); see also Symantec Corp. v.
Computer Assocs. Int'l Inc., 522 F.3d 1279, 1288 (Fed. Cir. 2008). We find
that the recitation “in which the correlation between successive pseudo-
random numbers is reduced” does not recite any essential steps and,
therefore, amounts to a mere statement of intended use. Accordingly,
consistent with the cited precedents, such recitation is not entitled to
patentable weight since it is held only in the preamble and does not breathe
life into the body of independent claim 1.
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Next, Meiyappan discloses providing the output of an LFSR to a
sampling switch. (FF 3.) Further, Meiyappan discloses periodically
clocking the output of the sampling switch into a random storage register.
(Id.) We find that Meiyappan’s disclosure of periodically clocking the
output of the sampling switch is a function of the sampling input provided
by the LFSR. Therefore, consistent with our claim construction supra, we
find that Meiyappan describes sampling an LFSR output sequence within a
specific period, interval of time, or number of clock cycles by way of using a
sampling switch. Consequently, we find that Meiyappan describes
“sampling output sequences of said linear feedback shift register with a
specified periodicity,” as recited in independent claim 1. It follows that the
Examiner has not erred in finding that Meiyappan anticipates independent
claim 1.
35 U.S.C. § 102(e) Rejection—Furuta
Claim 7
We find error in the Examiner’s anticipation rejection of independent
claim 7. Independent claim 7 recites, inter alia, “a first linear feedback shift
register” and “a second linear feedback shift register.”
At best, we find that Furuta discloses an LFSR that includes seven flip
flops. (FF 4.) Consequently, we agree with Appellants that Furuta’s
disclosure of an LFSR that includes seven flip-flops only amounts to a first
LFSR and, therefore, Furuta does not describe a second LFSR. (App. Br.
20; Reply Br. 29-32.) We note that while an ordinarily skilled artisan would
have appreciated that duplicating Furuta’s LFSR involves only routine skill
in the art, see In re Harza, 274 F.2d 669 (CCPA 1960), such a finding is
insufficient for anticipation. Moreover, we find that the Examiner’s stated
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position that each “flip flop” amounts to a separate and distinct LFSR (Ans.
12-13) is unreasonable in light of the plain meaning of the term “flip flop” in
an electrical context (i.e., a latch used to store state information). Therefore,
we find that the Examiner improperly relied upon Furuta’s disclosure to
describe the disputed claim limitations. It follows that Appellants have
shown that the Examiner erred in finding that Furuta anticipates independent
claim 7.
Claims 8-10
Since dependent claims 8-10 incorporate by reference the same claim
limitation as independent claim 7, we find that Appellants have also shown
that the Examiner erred in finding that Furuta anticipates these claims for the
same reasons set forth in our discussion of independent claim 7.
35 U.S.C. § 102(e) Rejection—Thomas
Claims 11
We do not find error in the Examiner’s anticipation rejection of
independent claim 11. Independent claim 11 recites, inter alia, “operating a
nonlinear operator on said pseudo-random number and one or more
operands.”
We begin our analysis by noting that the Examiner satisfies the
burden of establishing a prima facie case of anticipation. (Ans. 5.)
Moreover, the Examiner finds that Thomas’ disclosure of operating a non-
linear shift register (i.e., operator) in order to generate non-linear filtered
output on a random number and one or more operands (i.e., first and second
taps) describes the disputed claim limitation. (Id. at 14.) In response,
Appellants reiterate the textual portions of Thomas relied upon by the
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Examiner and generally allege that Thomas fails to describe the disputed
claim limitation. (App. Br. 24-27; Reply Br. 38-41.)
Since Appellants fail to provide any substantive analysis explaining
why the Examiner’s explicit fact finding is in error, we find that the weight
of the evidence favors the Examiner’s position. Therefore, we find that
Appellants have not shown reversible error4 in the Examiner's anticipation
rejection of independent claim 11.
Nonetheless, Thomas discloses generating non-linear filtered output
bits from shift registers by selecting a first and second tap of an LFSR. (FF
5.) Thomas also discloses generating a key stream from feedback taps in a
non-linear manner. (FF 6.) Consequently, we find that Thomas describes a
non-linear operator that generates a key stream (i.e., random numbers) using
one or more taps. Thus, we find that Thomas describes the disputed claim
limitation. It follows that Appellants have not shown that the Examiner
erred in finding that Thomas anticipates independent claim 11.
Claim 12 and 13
Appellants do not provide separate and distinct arguments for
patentability with respect to dependent claims 12 and 13. (See App. Br. 24-
27; Reply Br. 38-41.) Therefore, we select independent claim 11 as
representative of these cited claims. See 37 C.F.R. § 41.37(c)(1)(vii).

4 See In re Jung, 637 F.3d 1356, 1365-66 (Fed. Cir. 2011)(“Jung argues that
the Board gave improper deference to the examiner’s rejection by requiring
Jung to ‘identif[y] a reversible error’ by the examiner, which improperly
shifted the burden of proving patentability onto Jung. Decision at 11. This
is a hollow argument, because, as discussed above, the examiner established
a prima facie case of anticipation and the burden was properly shifted to
Jung to rebut it. . . . ‘[R]eversible error’ means that the applicant must
identify to the Board what the examiner did wrong . . . .”).
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Consequently, Appellants have not shown that the Examiner erred in
rejecting dependent claims 12 and 13 for the same reasons set forth in our
discussion of independent claim 11.
35 U.S.C. § 102(e) Rejection—Walmsley
Claim 17
We find error in the Examiner’s anticipation rejection of independent
claim 17. Independent claim 17 recites, inter alia, “varying the initial value
of said hashing function over time by way of a function operating on one or
more variables.”
At best, we find that Walmsley discloses a protocol that runs a hash
function on keys and compares the results against an internal checksum
value. (FFs 7 and 8.) However, we find that Walmsley’s hash function is
not a function of time. While Walmsley’s hash function may be capable of
varying its initial value over time by way of a function operating on one or
more variables (e.g., iteration number or current output state of an LFSR),
we find no such description in Walmsley to indicate that this course of
action is even contemplated. Such conjecture would therefore require us to
resort to speculation, unfounded assumptions, or hindsight reconstruction.
See In re Warner, 379 F.2d 1011, 1017 (CCPA 1967). We will not resort to
such speculation or assumptions to cure the deficiencies in the factual basis
in order to support the Examiner’s anticipation rejection. Consequently, we
find that the Examiner has not presented sufficient evidence to warrant that
the textual portions of Walmsley relied upon describe the disputed claim
limitation. It follows that Appellants have shown that the Examiner erred in
finding that Walmsley anticipated independent claim 17.
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35 U.S.C. § 103(a) Rejection—Combination of Furuta and Gressel
Claims 18 and 19
We find that Gressel does not remedy the above-noted deficiency in
the Examiner’s anticipation rejection of independent claim 7. Therefore,
since dependent claims 18 and 19 incorporate by reference the same claim
limitations as independent claim 7, we find that Appellants have shown that
the Examiner erred in concluding that the combination of Furuta and Gressel
renders these claims unpatentable for the same reasons set forth in our
discussion of independent claim 7.

V. CONCLUSIONS OF LAW
Appellants have not shown that the Examiner erred in rejecting: (1)
claim 1 under 35 U.S.C. § 102(e) as being anticipated by Meiyappan; and
(2) claims 11-13 under 35 U.S.C. § 102(e) as being anticipated by Thomas.
However, Appellants have shown that the Examiner erred in rejecting:
(1) claims 1-6, 14-16, and 20-22 under 35 U.S.C. § 102(e) as being
anticipated by Gressel; (2) claims 7-10 under 35 U.S.C. § 102(e) as being
anticipated by Furuta; (3) claim 17 under 35 U.S.C. § 102(e) as being
anticipated by Walmsley; and (4) claims 18 and 19 under 35 U.S.C. § 103(a)
as being unpatentable over the combination of Furuta and Gressel.

VI. DECISION
1. We affirm the Examiner’s decision to reject: (1) claim 1 under
35 U.S.C. § 102(e) as being anticipated by Meiyappan; and (2) claims 11-13
under 35 U.S.C. § 102(e) as being anticipated by Thomas.
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2. We reverse the Examiner’s decision to reject: (1) claims 1-6,
14-16, and 20-22 under 35 U.S.C. § 102(e) as being anticipated by Gressel;
(2) claims 7-10 under 35 U.S.C. § 102(e) as being anticipated by Furuta; (3)
claim 17 under 35 U.S.C. § 102(e) as being anticipated by Walmsley; and
(4) claims 18 and 19 under 35 U.S.C. § 103(a) as being unpatentable over
the combination of Furuta and Gressel.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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