Ex Parte Walter

Board of Patent Appeals and Interferences

May 19, 2010

11157994 (B.P.A.I. May. 19, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte HEINZ WALTER
____________

Appeal 2009-009034
Application 11/157,994
Technology Center 2800
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Decided: May 19, 2010
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Before JOHN C. MARTIN, MAHSHID D. SAADAT, and CARL W.
WHITEHEAD, JR., Administrative Patent Judges.

WHITEHEAD, JR., Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2009-009034
Application 11/579,994

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Appellant appeals under 35 U.S.C. § 134 from the Examiner’s
rejection of claims 1-14 and 21.1 App. Br. 1-2. We have jurisdiction under
35 U.S.C. § 6(b) (2002). We affirm.

STATEMENT OF THE CASE
Appellant invented a circuit arrangement for selective generation of
an analog current output value or an analog voltage output value as a
function of an analog input value.2

Claim 1, which further illustrates the invention, follows:
1. A circuit arrangement for selective generation of an analog current output
value or an analog voltage output value as a function of an analog input
value, the circuit arrangement comprising:
a current control unit;
a voltage control unit;
a current output source
a voltage output source; and
means for producing an analog input value and sending the analog
input value to an input of the current control unit and to an input of the
voltage control unit,
wherein the current output source is triggered by the current control
unit and the voltage output source is triggered by the voltage control unit,
and

1 Claims 15-20 has been objected to by the Examiner. See Final Rej. 6.
2 See App. Br. 2.
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wherein the current output source and the voltage output source are
triggered in parallel and are connected in series on their output sides.

The Rejection
The Examiner relies upon the following prior art references as
evidence of unpatentability:
Miller US 4,484,331 Nov. 20, 1984
Ooishi US 5,783,956 Jul. 21, 1998
Muyshondt US 6,316,991 B1 Nov. 13, 2001
Shih US 6,624,685 B2 Sep. 23, 2003

Claims 1-8, 13 and 14 stand rejected under 35 U.S.C. § 102(b) as
being unpatentable over Ooishi (Ans. 3-4).
Claims 1, 6 and 9 stand rejected under 35 U.S.C. § 102(b) as being
unpatentable over Shih (Ans. 4-5).
Claims 1, 6 and 9-11 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Miller and Shih (Ans. 5-6).
Claims 12 and 21 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Miller, Shih and Muyshondt (Ans. 6).
Claim 21 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ooishi and Muyshondt (Ans. 6-7).

Rather than repeat the arguments of Appellant or the Examiner, we
refer to the Appeal Brief (filed November 3, 2008), the Reply Brief (filed
January 22, 2009) and the Answer (mailed December 22, 2008) for their
respective details. In this decision, we have considered only those
arguments actually made by Appellant. Arguments which Appellant could
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have made but did not make in the Brief have not been considered and are
deemed to be waived. See 37 C.F.R. § 41.37(c)(1)(vii) (2008).

Anticipation rejection over Ooishi

ISSUE
Does Ooishi’s circuit arrangement generate an analog current output
value or an analog voltage output value as a function of an analog input
value?

FINDINGS OF FACT
1. Figure 5 of Ooishi is reproduced below:

Figure 5 discloses a circuit diagram showing the structure of the internal
power supply potential generating circuit 310a (Ooishi; col. 13, ll. 55-57).
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2. Ooishi discloses the employment of multiple nodes including an external
power supply node 300a, a ground node 300b, an internal power supply
node 300c and a current supply node 312 (col. 13, ll. 6-61).

3. Ooishi discloses wherein the differential amplifying circuit 314 compares
Vref and internal power supply potential intVcc for outputting a driver
control signal DRV corresponding to the difference between the two values.
When the intVcc is lower than Vref, the differential amplifying circuit
lowers the potential level of the driver control signal and if the intVcc is
higher than Vref, the differential amplifying circuit increases the driver
control signal. The driver control signal changes in an analog manner (col.
14, ll. 6-23).

PRINCIPLES OF LAW
“A claim is anticipated only if each and every element as set forth in
the claim is found, either expressly or inherently described, in a single prior
art reference.” Verdegaal Bros., Inc. v. Union Oil Co. of Cal., 814 F.2d 628,
631 (Fed. Cir. 1987).

ANALYSIS
Claim 1
Appellant argues that the Examiner’s statement indicating that Ooishi
shows a circuit arrangement for selective generation of either an analog
current value or analog voltage value as a function of an analog input value
is incorrect (App. Br. 3). Appellant further argues:
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Thus, the internal power supply potential generating circuit
310a does not have any node for any analog input value, does
not have any node for an analog current output value as a
function of an analog input value, and does not have any node
for an analog voltage output value as a function of an analog
input value. (App. Br. 5).

It is the Examiner’s position that the internal power supply
generating circuit has at least nodes 313a (Vref) and 300a (extVcc) for
analog input values, has an analog current output value Is (node 312)
as a function of an analog input value, and has an analog voltage
output value intVcc (node 300c) as a function of an analog input
value. See Ans. 7.
We agree with the Examiner that Ooishi’s analog current output value
Is and analog voltage output value intVcc are both functions of analog input
values Vref and extVcc. See FF 1; Ans. 3. The values of Is and intVcc are
determined in part by the values of Vref and extVcc, which is enough to
satisfy the broad “as a function” claim language. As the Examiner has stated
in his rejection, Ooishi discloses means for producing an analog input value
313 (reference potential generating circuit) and sending the signal to the
input of the current control unit 316b and the input of the voltage control
unit 314. See Ans. 3; See FF 1-3.
The Appellant also argues that the circuit arrangement in claim 1 will
yield an analog output value between 4 mA and 20 mA or an analog voltage
output between 0 V and 10 V based upon an analog input value between 0
mV and 100 mV (App. Br. 5; Reply Br. 2). However, this argument is not
commensurate in scope with the claim, which recites no specific values.
Furthermore, lawyer's arguments and conclusory statements that are
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unsupported by factual evidence have little probative value. In re Geisler,
116 F.3d 1465, 1470 (Fed. Cir. 1997); see also In re De Blauwe, 736 F.2d
699, 705 (Fed. Cir. 1984).
Therefore for the reasons we have stated above, we will sustain the
Examiner’s rejection of claim 1 over Ooishi.

Claims 2 and 7
Appellant argues that claim 2 distinguishes over Ooishi because the
internal power supply potential generating circuit 310a does not have a node
for an analog input value, does not have a node for an analog current output
value and does not have a node for an analog voltage output value (App. Br.
6). We do not find the Appellant’s arguments to be persuasive for the same
reasons as we stated above.
Appellant further notes that claim 7 recites when the analog voltage
output value is generated, the current output source makes available a load
current that flows over a load resistor and argues that since the claimed
analog voltage output value is not produced, no such load current can be
produced when the analog voltage output value is generated (App. Br. 7).
Appellant’s conclusion that Ooishi does not produce the claimed analog
voltage output value is unconvincing for the reasons given above.

Claims 3-6, 8, 13 and 14
Appellant does not separately argue with particularity the limitations
of claims 3-6, 8, 13 and 14 and therefore we sustain the Examiner’s rejection
of the claims for the reasons indicated previously.

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Anticipation rejection over Shih
ISSUE
Does Shih’s circuit arragement unit generate either an analog current
output value or an analog voltage output value as a function of the analog
input value?

FINDING OF FACTS
4. Figure 3 of Shih is reproduced below:

Figure 3 discloses a schematic diagram of a burn in reference circuit of a
level detector circuit (col. 3, ll. 63-67 – col. 4, ll. 1-26 – Shih).

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ANALYSIS
Claims 1, 6 and 9
Appellant argues:

Thus, the circuit arrangement disclosed in Fig. 3 of Shih
et al. does not have a lead (or node) for an analog input
value, does not have a lead (or node) for an analog
current output value as a function of an analog input
value, and does not have any lead (or node) for an
analog voltage output value as a function of an analog
input value. Since these are claimed aspects of the
present invention, the Shih et al. patent cannot be
anticipatory of claim 1 of the present application.

(App. Br. 8)(emphasis in original).
The Examiner contends that Shih’s figure 3 discloses the invention as
claimed including a voltage control source 315, 321, a current output source
325, a voltage output source 329 and means for producing analog input
value 302. See Ans. 4; FF 4. The analog values at both the analog current
output 325 and voltage output source 329 are determined in part by the
analog input value 302, which is broad enough to satisfy the broad “as a
function” claim language. Therefore Appellant’s arguments are not
persuasive and we will sustain the Examiner’s rejection of claim 1 for these
reasons and the reasons we stated previously.
Appellant does not separately argue with particularity the limitations
of claims 6 and 9 and therefore we sustain the Examiner’s rejection of the
claims for the reasons indicated previously.

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Obviousness rejection over Miller and Shih
Claims 1, 6 and 9-11
ANALYSIS

Appellant argues that Miller does not disclose means for producing an
analog input value (App. Br. 8). This argument is unpersuasive because
Appellant has not established that voltage VS is not an analog input value.

Appellant argues that figures 1 and 2 of Miller would be impossible
for one of ordinary skill in the art to combine with Shih’s figure 6 without
inventive effort (App. Br. 9). We do not find the Appellant’s argument
persuasive because Appellant failed to provide a specific reason or rationale
as to why the combination of Miller and Shih would require inventive effort
or undue experimentation.
Appellant also argues that like Ooishi and Shih, Miller does not
disclose a circuit arrangement for selective generation of an analog current
output value or an analog voltage output value as a function of an analog
input value. See App. Br. 9. Claim 1 recites “selective generation of an
analog current output value or an analog voltage output value as a function
of an analog input value.” Therefore, we do not find the Appellant’s
arguments persuasive because as the Examiner has indicated, Miller
discloses means for producing at least an analog output value R2 and Q1 as
a function of the analog input value Vs and S. See Ans. 5. Additionally, the
Examiner relies upon Shih to disclose an analog current output that is a
function of an analog input value. Id.
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Further, Appellant argues that none of the references disclose that the
current output source and the voltage output source are triggered in parallel
and are connected in series on their output sides as set forth in claim 1. Id.
This argument is merely a recitation of claim language without being
accompanied by an explanation of why the recited limitation is not disclosed
or suggested by the references. That is, Appellant’s arguments are merely
general statements and do not address the combination of Miller and Shih as
presented by the Examiner, especially since the Examiner clearly relies upon
Shih’s figure 3 and not Shih’s figure 6 as argued by the Appellant. See Ans.
5. We will sustain the Examiner’s rejection of claims 1, 6 and 9-11.

Obviousness rejections over Miller, Shih, Ooishi and Muyshondt
Claims 12 and 21
The Appellant argues the claims 12 and 21 in two separate groups
(App. Br. 9-10). We group these claims together here for clarity and brevity
since Appellant has not presented any patentability arguments that
specifically state how each of the claims is patentable over the prior art of
record. Therefore we will sustain the Examiner’s rejection of claims 12 and
21.
DECISION
We affirm the Examiner’s 35 U.S.C. § 102(b) rejection of claims 1-8,
13 and 14 as anticipated by Ooishi.
We affirm the Examiner’s 35 U.S.C. § 102(b) rejection of claims 1, 6
and 9 as anticipated by Shih.
We affirm the Examiner’s 35 U.S.C. § 103(a) rejection of claims 1, 6
and 9-11 as being unpatentable over Miller and Shih.
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We affirm the Examiner’s 35 U.S.C. § 103(a) rejection of claims 12
and 21 as being unpatentable over Miller, Shih and Muyshondt.
We affirm the Examiner’s 35 U.S.C. § 103(a) rejection of claim 21 as
being unpatentable over Ooishi and Muyshondt.

TIME PERIOD
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(v) (2009).

ORDER

AFFIRMED

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ROBERTS MLOTKOWSKI SAFRAN & COLE, P.C.
Intellectual Property Department
P.O. Box 10064
MCLEAN, VA 22102-8064

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