Ex Parte Vlasenko et al

Patent Trial and Appeal Board

Feb 8, 2017

14092788 (P.T.A.B. Feb. 8, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/092,788 11/27/2013 Peter Vlasenko 01160-US-CON5 8247
68256 7590 02/10/2017
Conversant Intellectual Property Management Inc.
5601 Granite Parkway
Suite 1300
Plano, TX 75024
EXAMINER
ODOM, CURTIS B
ART UNIT PAPER NUMBER
2631
NOTIFICATION DATE DELIVERY MODE
02/10/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ipadmin @ conversantip. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PETER VLASENKO AND DIETER HAERLE
Appeal 2016-005651
Application 14/092,788
Technology Center 2600
Before BRADLEY W. BAUMEISTER, JON M. JURGOVAN, and
AARON W. MOORE Administrative Patent Judges.
JURGOVAN, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2016-005651
Application 14/092,788
STATEMENT OF THE CASE
Appellants1 seek review under 35 U.S.C. § 134(a) from the
Examiner’s Final Rejection of claims 3—12. Claims 1 and 2 are cancelled.
We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.2
CLAIMED INVENTION
The claims are directed to a wide frequency range delay locked loop
(“DLL”). (Spec. Title.) Claim 3, reproduced below with argued language
shown in italics, is illustrative of the claimed subject matter:
3. A delay locked loop comprising:
first circuitry configured to detect when an internal clock
signal is within a phase detection window; and
second circuitry configured to detect when the internal
clock signal is in phase with an external clock signal;
a first delay circuit configured to provide coarse phase
adjustment in the delay locked loop until the internal clock signal
is in phase with the external clock signal, the first delay circuit
comprising a plurality of delay elements; and
a counter configured to control what number of the delay
elements are enabled, and the counter being further configured
to have an initial value which corresponds to an at least
substantially minimum delay of the first delay circuit,
wherein the second circuitry is configured to output a
control signal to hold the first delay circuit at a fixed delay while
a second delay circuit provides fine phase adjustment in the delay
locked loop.
(App. Br. 9 — Claims App’x.)
1 The Appeal Brief identifies Conversant Intellectual Property Management
Inc. as the real party in interest. (App. Br. 2.)
2 Our Decision refers to the Specification filed November 27, 2013
(“Spec.”), the Final Office Action mailed March 18, 2015 (“Final Act.”), the
Appeal Brief filed September 15, 2015 (“App. Br.”), and the Examiner’s
Answer mailed March 7, 2016 (“Ans.”).
2
Appeal 2016-005651
Application 14/092,788
REJECTIONS
Claims 3—6, 8, and 10 stand rejected under 35 U.S.C. § 103(a) based
on Chengson (US 5,790,612, issued Aug. 4, 1998) and Shibayama
(US 6,346,837 Bl, issued Feb. 12, 2002). (Final Act. 3-5.)
Claims 7, 9, 11, and 12 stand rejected under 35 U.S.C. § 103(a) based
on Chengson, Shibayama, and Oh (US 6,765,976 Bl, issued July 20, 2004).
(Final Act. 5—6.)
ANALYSIS
Independent Claim 3
Appellants argue “the Examiner has incorrectly concluded that
Shibayama discloses a ‘counter . . . configured to have an initial value which
corresponds to an at least substantially minimum delay of the first delay
circuit’,” as recited in claim 3. (App. Br. 4—5, citing Shibayama 4:25—28.)
Specifically, Appellants argue that, although the Examiner is correct that
the state “0” of the ring counter 31 in Shibayama corresponds to at least
substantially minimum delay Tc, there is no disclosure in Shibayama that the
state “0” of the ring counter 31 is an “initial value.” (Id.) Appellants argue
Shibayama is completely silent on providing any teachings of the behavior
of the disclosed DLL during initialization. (Id.)
To the contrary, the Examiner finds this limitation is taught by
Shibiyama in the following passage:
The ring counter 31 is an up/down 8-ary ring counter without a
decoding function. That is, when the control signal UP-C is “1”,
the state of the ring counter 31 is changed from state “0” via
state “1”, state “2”,... to state “7” as shown in FIG. 7A. On the
other hand, when the control signal DOWN-C is “1”, the state of
the ring counter 31 is changed from state “7” via state “6”, state
“5”,... to state “0” as shown in FIG. 7A.
3
Appeal 2016-005651
Application 14/092,788
(Shibayama 4:25—32, emphasis added.) The Examiner views Shibayama’s
state “0” in the count-up scenario where control signal UP-C is 1 as the
claimed “initial value.” (Final Act. 4; Ans. 8.)
We agree with the Examiner’s finding. Shibayama’s count-up
scenario begins from state “0,” which, thus, may be regarded an “initial
value” under the standard of broadest reasonable interpretation. See In re
Am. Acad. ofSci. Tech. Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004) (“[T]he
PTO is obligated to give claims their broadest reasonable interpretation
during examination.”). One of ordinary skill in the art, reading Shibayama’s
disclosure, would have understood that the counter must be configured with
state “0” before the counter begins counting up. State “0” is, thus, an “initial
value” within the meaning of the claimed terminology, and we are not
persuaded by Appellants’ arguments that the Examiner errs in the rejection.
Appellants state that DFFs with the claimed features have been
introduced to the market by well-known manufacturers after the priority date
of the subject application. (App. Br. 7.) We interpret Appellants’ statement
to be an assertion that the claimed invention has attained commercial success
in the market, and is thus nonobvious. See Graham v. John Deere Co., 383
U.S. 1, 17—18 (1966) (recognizing commercial success as one of the
secondary considerations that can be used to demonstrate a claim is
nonobvious). However, Appellants identify no evidence in the record, but
offer only argument, to support their contention. Mere attorney argument is
insufficient to show evidence of circumstances justifying reversal of the
Examiner’s rejections. See In re Huang, 100 F.3d 135, 139-140 (Fed. Cir.
1996); In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir. 1997). Accordingly,
we sustain the Examiner’s rejection.
4
Appeal 2016-005651
Application 14/092,788
Remaining Claims
The remaining claims depend from independent claim 3 and are
argued on the same basis. (App. Br. 7). For the stated reasons, we sustain
the rejections of these claims. 37 C.F.R. § 41.37(c)(l)(iv).
DECISION
We affirm the Examiner’s rejections of claims 3—12 under 35 U.S.C.
§ 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
5