Ex Parte Vivet et al

Patent Trials and Appeals Board

May 20, 2019

15068899 - (D) (P.T.A.B. May. 20, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
15/068,899 03/14/2016
125968 7590 05/22/2019
V orys, Sater, Seymour and Pease LLP
(ImgTec)
1909 K St., N.W.
Ninth Floor
Washington, DC 20006
FIRST NAMED INVENTOR
Marc Vivet
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
070852.000257 2284
EXAMINER
DUNPHY, DAVID F
ART UNIT PAPER NUMBER
2668
NOTIFICATION DATE DELIVERY MODE
05/22/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patlaw@vorys.com
vmdeluca@vorys.com
vorys _ docketing@cardinal_ip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte J'vIARC VI VET' and PAUL BRASNETT
Appeal 2018-008114
Application 15/068,899
Technology Center 2600
Before ALLEN R. MacDONALD, MICHAEL J. ENGLE,
and IFTIKHAR AHMED Administrative Patent Judges.
MacDONALD, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's final
rejection of claim 20. Appellants have cancelled claim 7, and claims 1-6
and 8-19 are indicated as allowable. App. Br. 1 (Appeal Brief filed March
5, 2018, "App. Br."). We have jurisdiction under 35 U.S.C. § 6(b ).
We REVERSE, and we NEWLY REJECT claims 11-18 and 20.
1 Appellants identify Imagination Technologies Limited as the real party in
interest. App. Br. 1.
Appeal 2018-008114
Application 15/068,899
Claim 20
Claim 20 is the sole claim under appeal and reads as follows
( emphasis, formatting, and bracketed material added):
20. A non-transitory computer readable storage medium having
stored thereon a computer readable description of an integrated
circuit that, when processed in an integrated circuit manufacturing
system, causes the integrated circuit manufacturing system to
manufacture a processing module comprising:
[A.] alignment logic configured to:
[i.] apply respective transformations to at least some of
the images of the set to bring them closer to
alignment with the reference image from the set of
images,
[ii.] wherein the transformations are determined using
multiple kernel tracking to initialize a Lucas
Kanade Inverse algorithm that is used on said at
least some of the images to bring them closer to
alignment with said reference image; and
[B.] combining logic configured to:
[i.] combine a plurality of images including said one or
more of the transformed images to form a reduced
n01se image.
Rejection
The Examiner rejects claim 20 under 35 U.S.C. § 112(a) as failing to
comply with the enablement requirement. Final Act. 9--11 (Final Office
Action, mailed October 19, 2017, "Final Act.").
Issue on Appeal
Did the Examiner err in rejecting claim 20 as failing to comply with
the enablement requirement?
2
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Application 15/068,899
PRINCIPLES OF LAW
Undue Experimentation- Wands Factors
Whether undue experimentation is needed is not a single, simple
factual determination, but rather is a conclusion reached by weighing many
factual considerations. In re Wands, 858 F.2d 731, 737 (Fed. Cir. 1988).
The Wands factors include:
(1) the quantity of experimentation necessary, (2) the amount of
direction or guidance presented, (3) the presence or absence of
working examples, ( 4) the nature of the invention, ( 5) the state
of the prior art, ( 6) the relative skill of those in the art, (7) the
predictability or unpredictability of the art, and (8) the breadth of
the claims.
Id. ( citations omitted).
In reviewing for lack of enablement, the Wands court elected to
consider "all of the factors." Id. at 740. However, it is not necessary to
review all the Wands factors to find a disclosure enabling. Rather, the
Wands factors "are illustrative, not mandatory" and what is relevant to an
enablement determination depends upon the facts of the particular case. See
Amgen, Inc. v. Chugai Pharm. Co., 927 F.2d 1200, 1213 (Fed. Cir. 1991);
see also Enzo Biochem, Inc. v. Calgene, Inc., 188 F.3d 1362, 1371 (Fed. Cir.
1999); Warner-Lambert Co. v. Teva Pharms. USA, Inc., 418 F.3d 1326,
1337 (Fed. Cir. 2005).
EXAMINER'S ANALYSIS
The Examiner rejected claim 20 under 35 U.S.C. § 112(a) by
considering the Wands factors (Final Act. 10) and stating:
In particular, these claims recite a "description of an integrated
circuit" disclosed in FIG. 10 of the drawings merely by a block
diagram with the functional label, "IC definition dataset."
3
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Application 15/068,899
Applicant provides neither schematic nor written description of
an actual electrical circuit. The disclosure of an electrical circuit
apparatus, depicted in the drawings by block diagrams with
functional labels is nonenabling. MPEP § 2164.06(a)(I) citing,
In re Gunn, 537 F.2d 1123, 1129, 190 USPQ 402, 406 (CCP A
1976).
Final Act. 10-11.2
The Examiner also determined:
[M]erely identifying software that might be used to invent a
"description of an integrated circuit" is not the same thing as
enabling an invention of that circuit. ... Applicant has provided
no timing diagrams, descriptions or working examples of any
register transfer level (RTL) code, or RTL schematics, from
which the recited integrated circuit might be manufactured.
Appellant[s'] disclosure is little more than an invitation to those
skilled in the art to experiment extensively with Hardware
Description Language (HDL ).
Ans. 6 ( emphasis omitted). 3
By way of illustration, and not as evidence, Quadrature
Phase Shift Keying (QPSK) was a well known modulation
technique in 2017. Yet, the International J oumal of Computer
Applications published an entire article that year about
implementing the technique in a Hardware Description
Language (HDL) software application (i.e., Verilog). In the
article, "FPGA Implementation of Digital Modulation
Techniques BPSK and QPSK using HDL Verilog" by Tanawade
et al, the authors did not merely provide a block diagram
overview of Hardware Description Languages (HDL). Instead,
the authors enabled readers to practice QPSK in HDL by, for
2 Although not explicitly stated, this analysis may correspond to Wands
factors (2) the amount of direction or guidance presented and (3) the
presence or absence of working examples.
3 Although not explicitly stated, this analysis may correspond to Wands
factors (2) the amount of direction or guidance presented and (3) the
presence or absence of working examples.
4
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Application 15/068,899
example, disclosing timing diagrams (see, FIGS. 6, 7, 8, 9, on
pp. 46-48) and RTL schematic diagrams (see, FIGS. 10, 11, on
pp. 48-49) that were particular to the circuit being designed.
Ans. 7 ( emphasis omitted). 4
Conversely, Applicant discloses implementing his technique in a
Hardware Description Language (HDL) software application
with little more than a single block in a functional block diagram
and an overview of Hardware Description Language (HDL)
itself. This block diagram, unrelated to the specifics of the circuit
recited in the functional limitations of claim 20, was insufficient
to enable the manufacture of an actual electrical circuit capable
of performing those specific functions.
Ans. 7. 5
Although the structure recited in claim 20 is a[] "description of
an integrated circuit" stored in a computer readable medium that
"description of an integrated circuit" is subject to a functional
limitation that it causes the manufacture an actual electrical
circuit capable of performing specific image processing
functions. Thus, the [A]pplicant's disclosure must enable the
manufacturing of an actual electrical circuit capable of
performing all of the functions recited in claim 20. Moreover,
Applicant is not required to provide a schematic of an electrical
circuit, Applicant need merely enable an electrical circuit.
Ans. 8 ( emphasis omitted). 6
Certain Wands factors, such as the amount of direction provided
by the inventor (none), the existence of working examples (none)
and the quantity of experimentation, were discussed with
particularity in paragraph 19 of p. 10, because these factors were
4 Although not explicitly stated, this analysis may correspond to Wands
factors (5) the state of the prior art and (6) the relative skill of those in the
art.
5 Although not explicitly stated, this analysis may correspond to Wands
factor (8) the breadth of the claims.
6 Although not explicitly stated, this analysis may correspond to Wands
factor (4) the nature of the invention.
5
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Application 15/068,899
particularly lacking in Applicant's disclosure. For example, the
final rejection considered the amount of direction provided by
the inventor (none) when it observed, "[T]hese claims recite a
'description of an integrated circuit' disclosed in FIG. 10 of the
drawings merely by a block diagram with the functional label,
[']IC definition dataset.[']" The final rejection considered the
existence of working examples (none) when it observed that,
"Applicant provides neither schematic nor written description of
an actual electrical circuit."
Ans. 8-9. As stated, this analysis corresponds to Wands factors (1) the
quantity of experimentation necessary, (2) the amount of direction or
guidance presented, and (3) the presence or absence of working examples.
Applicant omits mention of the functional limitations of the
"description of an integrated circuit", which recite the
manufacture of an unconventional circuit. The issue is not
whether the structures [ cited by Appellants] were known in the
art. If one ignores the functional limitations of claim 20, of
course these structures were known in the art. However, claim
20 attaches specific functional limitations to the "description of
an integrated circuit," among which are that it, "causes the
integrated circuit manufacturing system to manufacture" an
actual circuit capable of performing specific image processing
functions. Thus, the issue is whether the actual circuit recited in
claim 20, which is manufactured using the above "description of
an integrated circuit," was known in the art.
Ans. 9-10 (emphasis omitted). 7
PANEL'S ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
arguments that the Examiner has erred.
7 Although not explicitly stated, this analysis may correspond to Wands
factor (7) the predictability or unpredictability of the art.
6
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Application 15/068,899
I. Analysis of Appellants 'First Argument
Appellants contend that the Examiner erred in rejecting claim 20
under 35 U.S.C. § 112(a) because the Specification provides full enablement
of claim 20. App. Br. 3.
In the Examiner discussions cited supra, the Examiner only minimally
connects the analysis to corresponding Wands factors (1 }-(8). While we
might be able to speculatively connect the Examiner's analysis to particular
Wands factors (noted supra at footnotes 2-7), we decline to do so.
Therefore, as to Appellants' first argument, due to the indefiniteness of
claim 20 (discussed infra) and the lack of certainty as to the Examiner's
intended alignment of the rejection analysis to the Wands factors (noted
supra at footnotes 2-7), we are unable to determine whether this claim is
unpatentable under 35 U.S.C. § 112(a) for lack of an enabling disclosure
commensurate with the scope of the claim. Therefore, we reverse this
rejection proforma.
2. Analysis of Appellants' Second Argument
Appellants contend that the Examiner erred in rejecting claim 20
under 35 U.S.C. § 112(a) because the rejection of claim 20 is contrary to
public policy and inconsistent with existing determinations of the office as to
U.S. Patent No. 9,760,997. App. Br. 7.
This contention presents us with arguments regarding the impact of
other patents with respect to the 35 U.S.C. § 112(a) enablement rejection of
present claim 20. The Court of Customs and Patent Appeals, predecessor
court to the Court of Appeals for the Federal Circuit, held that"[ e Jach case
is determined on its own merits. In reviewing specific rejections of specific
claims, this court does not consider allowed claims in other applications or
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Application 15/068,899
patents." In re Gyurik, 596 F.2d 1012, 1018 n.15 (CCPA 1979) (citations
omitted). As our reviewing court directs, we will not consider the allowed
claims in other patents when determining whether the present claim is
enabled. It follows that this argument does not show the Examiner has
erred.
NEW GROUNDS OF REJECTION
Pursuant to our authority under 37 C.F.R. § 4I.50(b), we reject claims
11-18 and 20 under 35 U.S.C. § 112(a), as being indefinite.
In claim 20, "the images," "the set," and "the reference image" lack
any antecedent basis. Similarly in claim 11, "the reference image" lacks any
antecedent basis. Claims 12-18 incorporate by dependency the
indefiniteness of claim 11.
CONCLUSIONS
(1) The Appellants have shown the Examiner erred in rejecting claim
20 under 35 U.S.C. § 112(a) as failing to comply with the enablement
requirement.
(2) We newly reject claims 11-18 and 20 under 35 U.S.C. § 112(b) as
being indefinite.
(3) Claims 11-18 and 20 are not patentable.
DECISION
The Examiner's rejection of claim 20 is reversed.
Claims 11-18 and 20 are newly rejected.
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Appeal 2018-008114
Application 15/068,899
37 C.F.R. § 41.50(b)
This decision contains a new ground of rejection pursuant to
37 C.F.R. § 4I.50(b), which provides that "[a] new ground of rejection
pursuant to this paragraph shall not be considered final for judicial review."
Section 41.50(b) also provides that Appellants, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of
the following two options with respect to the new grounds of rejection to
avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new Evidence relating
to the claims so rejected, or both, and have the matter
reconsidered by the examiner, in which event the prosecution
will be remanded to the examiner ....
(2) Request rehearing. Request that the proceeding be
reheard under § 41.52 by the Board upon the same Record ....
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
REVERSED
37 C.F.R. § 4I.50(b)
9