Ex Parte Vig et al

Board of Patent Appeals and Interferences

Aug 17, 2012

11435917 (B.P.A.I. Aug. 17, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte NITIN VIG and ARNAB K. MITRA
____________

Appeal 2010-000487
Application 11/435,917
Technology Center 2800
____________

Before JOHN A. JEFFERY, BRUCE R. WINSOR,
and ANDREW CALDWELL, Administrative Patent Judges.

WINSOR, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-000487
Application 11/435,917

2
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-6, 8, 9, 13-15, and 17-20. Claims 7, 10-12, and 16 have been
objected to, but are indicated as having allowable subject matter (Fin. Rej.
8). We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

STATEMENT OF THE CASE
“[Appellants’] disclosure relates to digital electronic devices and more
particularly to digital latches.” (Spec. ¶ [0001]).
A device and associated method to reduce hold-time
violations are disclosed. The device includes a latch module
with a selectable delay. The latch module includes a control
input to select the delay through the latch. In one embodiment,
the delay of the latch is the time between when a latching edge
of a clock signal is experienced by the latch until data changes
at the output of the latch. In the event of a hold-time violation
at latches that are downstream of other latches, a longer delay
can be selected at an upstream latch to provide a slower delay
path for data provided to the downstream latch violating the
hold-time. By providing a slower delay path, the data being
latched at the downstream latch will not change as quickly after
a latching signal is received, and therefore the possibility of a
hold-time violation is reduced.
(Abstract). Claim 1, which is illustrative of the invention, reads as follows
(emphasis added):
1. A method, comprising:
receiving a first control signal at a first latch device;
selecting a first delay through the first latch device for
signals at an input of the first latch device in
response to the first control signal being at a first
state; and
Appeal 2010-000487
Application 11/435,917

3
selecting a second delay through the first latch device for
signals at the input of the first latch device in
response to the first control signal being at a
second state.
Claims 1-4, 8, 9, 13-15, 19, and 20 stand rejected under 35 U.S.C.
§ 102(b) as anticipated by Callahan (US 5,525,921; June 11, 1996). (Ans. 3-
6).
Claims 5, 6, 17, and 18 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over by Callahan and Lee (US 2003/0200380 A1; Oct. 23,
2003). (Ans. 7-9).
Rather than repeat the arguments here, we refer to the Briefs (App. Br.
filed June 18, 2009; Reply Br. filed Sept. 21, 2009)1 and the Answer (Ans.
mailed July 20, 2009) for the respective positions of Appellants and the
Examiner.

ISSUE
The pivotal issue2 raised by Appellants’ contentions is as follows:
Does Callahan disclose “selecting a second delay through the first
latch device for signals at the input of the first latch device in response to the
first control signal being at a second state” as recited in claim 1?

1 The Appeal Brief filed April 20, 2009, has not been considered as it is
deemed to have been superseded by the Appeal Brief filed June 18, 2009.
2 Appellants’ arguments present additional issues. We are persuaded of
Examiner error regarding this issue, which is dispositive of the appeal.
Therefore, we do not reach the additional issues.
Appeal 2010-000487
Application 11/435,917

4
ANALYSIS
Rejection under 35 U.S.C. § 102(b)
The Examiner finds that Callahan discloses all of the elements of
claim 1 in the first latching circuit illustrated in Callahan’s Figure 3 (Ans. 3-
4). The relevant portion of Callahan’s Figure 3 is reproduced here:

A portion of Callahan’s Figure 3 illustrating a schematic
diagram of a clocked latch circuit (see Callahan col. 2, ll. 56-59;
col. 4, l. 54–col. 5, l. 47).
The Examiner explains as follows:
The first delay would occur in response to 318 and 328, where
318 is on and 328 is off, thus causing the delay path through
320, which has an inherent delay. The second delay would
occur in response to 318 and 328, where 318 is off and 328 is
on, thus causing the delay path through 320, 324, and 320 [sic].
Both delays are connected to input through transistor 316.
(Ans. 10).
Appellants contend as follows:
Appeal 2010-000487
Application 11/435,917

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[W]hen the clock signal at terminal 318 is off, transistor 316 is
non-conductive, so that the input terminal 314 is isolated from
the inverter 320, as explicitly stated in Callahan: “During the
subsequent LOW half of its cycle, the square-wave clock signal
02 closes the first transmission-gate transistor 316 so that the
input terminal to the first inverter 320 is isolated from the
input terminal 314 of the CMOS clocked latch circuit 312.”
Callahan, column 5, lines 23-28 (emphasis added). Thus,
contrary to the Examiner’s assertion, when 318 is off and 328 is
on, there is no path for a signal to be conducted through the
latch for signals at the input 314 to the output 330.
Accordingly, Callahan fails to disclose both a first delay
through the latch device and a second delay through the latch
device, as provided by claim 1.
(Reply Br. 2-3). While we agree with the Examiner that Callahan discloses
a first delay through a latch device, we agree with Appellants, for the
reasons stated in Appellants’ Briefs (App. Br. 4-8; Reply Br. 2-3), that the
cited portions of Callahan do not disclose “selecting a second delay through
the first latch device” (emphasis added), as recited in claim 1.
Appellants have persuaded us of error in the Examiner’s rejection of
claim 1 as anticipated by Callahan. Accordingly, we will not sustain the
rejection of (1) claim 1; (2) claim 14, which includes a limitation
substantially similar to the limitation we find to not be disclosed by the cited
portions of Callahan (see App. Br. 8-9); (3) claims 2-4, 8, 9, and 13, which
depend from claim 1 (see App. Br. 9-11); and (4) claims 15, 19, and 20,
which depend from claim 14 (see App. Br. 11).
Rejection under 35 U.S.C. § 103(a)
Claims 5 and 6 depend from claim 1 and claims 17 and 18 depend
from claim 14 (see App. Br. 11-12). The Examiner has not identified any
passages in Lee that teach the limitation we find supra to not be disclosed by
Appeal 2010-000487
Application 11/435,917

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Callahan (see id.; Ans. 13). Accordingly, we will not sustain the rejection of
claims 5, 6, 17, and 18 as unpatentable over Callahan and Lee.

ORDER
The decision of the Examiner to reject claims 1-6, 8, 9, 13-15, and 17-
20 is reversed.

REVERSED

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