Ex Parte Vellianitis

Patent Trial and Appeal Board

Jan 30, 2018

14718125 (P.T.A.B. Jan. 30, 2018)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/718,125 05/21/2015 Georgios VELLIANITIS P20110657US01/1085.01476 5861
54657 7590 01/30/2018
DUANE MORRIS LLP (TSMC)
IP DEPARTMENT
30 SOUTH 17TH STREET
PHILADELPHIA, PA 19103-4196
EXAMINER
TRAN, TONY
ART UNIT PAPER NUMBER
2894
MAIL DATE DELIVERY MODE
01/30/2018 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte GEORGIOS VELLIANITIS1
Appeal 2017-004795
Application 14/718,125
Technology Center 2800
Before KAREN M. HASTINGS, CHRISTOPHER C. KENNEDY, and
MONTE T. SQUIRE, Administrative Patent Judges.
SQUIRE, Administrative Patent Judge.
DECISION ON APPEAL2
Appellant appeals the Examiner’s decision finally rejecting claims 1—
12, 18, and 19.3 35 U.S.C. § 134(a). We have jurisdiction under 35 U.S.C.
§ 6(b).
1 Appellant is Applicant, Taiwan Semiconductor Manufacturing Co., Ltd.,
which, according to the Appeal Brief, also is the real party in interest.
App. Br. 3.
2 In our Decision, we refer to the Specification filed May 21, 2015 (“Spec.”);
Final Office Action dated March 8, 2016 (“Final Act.”); Appeal Brief filed
July 28, 2016, as corrected October 10, 2016 (“App. Br.”); Examiner’s
Answer to the Appeal Brief dated November 25, 2016 (“Ans.”); and Reply
Brief dated January 20, 2017.
3 Pending claims 13—17 and 20 are withdrawn. Final Act. 1.
Appeal 2017-004795
Application 14/718,125
We AFFIRM.
The Claimed Invention
Appellant’s disclosure relates to semiconductor integrated circuit
fabrication technology for metal oxide semiconductor transistors. Spec. 12.
Claim 1 is illustrative of the claimed subject matter on appeal and is
reproduced below from the Claims Appendix to the Appeal Brief (App. Br.
10) (key disputed claim language italicized and bolded):
1. A method of fabricating oxide/semiconductor
interface comprising:
receiving a semiconductor substrate having a
surface;
depositing a layer of metal on the semiconductor
surface, wherein the layer of metal is deposited in a
non-oxidized state', and
depositing a layer of high-k oxide material on the
layer of metal by an atomic layer deposition process,
whereby the layer of metal oxidizes from exposure to the
atomic layer deposition process’ oxidizing agents O3 and
H20 during the deposition of the high-k oxide material,
thus forming a high-k metal oxide layer at an interface
between the semiconductor substrate and the layer of
high-k oxide material and prevents formation of
undesirable low-k oxide interfacial layer.
The References
The Examiner relies on the following prior art references as evidence
in rejecting the claims on appeal:
Choi et al., US 2009/0309187 A1 Dec. 17, 2009
(hereinafter “Choi”)
Saitoh et al., US 2012/0146053 Al June 14, 2012
(hereinafter “Saitoh”)
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Application 14/718,125
Chenetal., US 2012/0322220 A1 Dec. 20, 2012
(hereinafter “Chen”)
The Rejections
On appeal, the Examiner maintains (Ans. 3) the following rejections:
1. Claims 1—7 and 10-12 are rejected under pre-AIA
35 U.S.C. § 102(b) as being anticipated by Choi (“Rejection 1”).
Final Act. 2.
2. Claims 8 and 9 are rejected under pre-AIA 35 U.S.C. § 103(a)
as being unpatentable over Choi in view of Saitoh (“Rejection 2”).
Final Act. 5.
3. Claims 18 and 19 are rejected under pre-AIA
35 U.S.C. § 103(a) as being unpatentable over Choi in view of Chen
(“Rejection 3”). Final Act. 6.
OPINION
Having considered the respective positions advanced by the Examiner
and Appellant in light of this appeal record, we affirm the Examiner’s
rejections based on the fact finding and reasoning set forth in the Answer
and Final Office Action, which we adopt as our own.
We highlight and address specific findings and arguments below for
emphasis.
Rejection 1
Claims 1—5
Appellant argues claims 1—5 as a group. App. Br. 6—7. We select
independent claim 1 as representative, and dependent claims 2—5 stand or
fall with claim 1. 37 C.F.R. § 41.37(c)(l)(iv).
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Application 14/718,125
The Examiner determines that Choi discloses a method of fabricating
oxide/semiconductor interface satisfying all of the steps of claim 1 and thus,
anticipates the claim. Final Act. 2—3 (citing Choi, Fig. 3, Tflf 37, 38, 50—52,
58).
Appellant argues that the Examiner’s rejection of claim 1 should be
reversed because Choi does not disclose the “depositing a layer of metal on
the semiconductor surface, wherein the layer of metal is deposited in a non-
oxidized state” and “depositing a layer of high-k oxide material on the layer
of metal by an atomic layer deposition process, whereby the layer of metal
oxidizes . . . during the deposition of the high-k oxide material” steps of
claim 1. App. Br. 6—7. In particular, Appellant contends that the dielectric
layer 112 of Choi is not metal in a “non-oxidized state” (App. Br. 6) and, as
a result, Choi’s deposition step is “not the same” as the step of depositing a
layer of metal on the semiconductor surface, wherein the layer of metal is
deposited in a non-oxidized state recited in the claim {id. at 7).
Appellant further contends that because Choi does not disclose the
first claim step of depositing a layer of metal in a non-oxidized state, the
reference cannot disclose the second claim step of depositing a layer of high-
k oxide material on the layer of metal, whereby the layer of metal oxidizes
during the deposition of the high-k oxide material. App. Br. 7.
We do not find Appellant’s arguments persuasive of reversible error
in the Examiner’s rejection. To serve as an anticipatory reference, “the
reference must disclose each and every element of the claimed invention.”
In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009).
Based on the record before us, we find that a preponderance of the
evidence supports the Examiner’s determination that Choi discloses each
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Application 14/718,125
and every element of claim 1, including the “depositing” steps. Choi, Fig. 3,
1137,38, 50-52,58.
Regarding the first depositing step, as the Examiner finds (Ans. 4),
Choi discloses depositing a layer of metal (Zr or Al) on a semiconductor
surface (100 + 110), wherein the layer of metal (112) is deposited in a non-
oxidized state (deposited as either ZrCU or A1NX). Choi, Fig. 3, H 40-41,
47. In particular, as the Examiner finds (Ans. 4—5), Choi discloses that the
first dielectric layer 112 may be formed by chemical vapor deposition
(CVD) or atomic layer deposition (ALD) and may be obtained from a
zirconium halide such as “ZrCU” or “an aluminum nitride layer (A1NX).”
Choi 1138, 40,41,47.
Regarding the second depositing step, as the Examiner finds (Ans. 5),
Choi discloses depositing a layer of high-k oxide material (114) on the layer
of metal by an atomic layer deposition process, whereby the layer of metal
oxidizes from exposure to the atomic layer deposition process’ oxidizing
agents O3 and H20 during the deposition of the high-k oxide material. Choi
1138, 50—52, 58. In particular, as the Examiner finds (Ans. 5), Choi
discloses that the deposition of layer 114 may be formed by an ALD
process, and the ALD process for forming the layer 114 “may include a
sequence of a metal precursor pulse/an oxidizing agent pulse” over the layer
of metal 112. Choi H 50-52, 58.
Choi further discloses that
The oxidizing agent may be oxygen (02) or ozone (O3).
In other example embodiment, the oxidizing agent may be
H2O, H202, or NO or an alcohol such as isopropyl alcohol,
methanol, or ethanol, which contain oxygen.
Choi 142 (emphasis added).
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Moreover, as the Examiner finds (Ans. 5), Choi discloses that the
layer of metal 112 oxidizes from exposure to the ALD process’ oxidizing
agents O3 and H20 during deposition of the high-k material—forming a
high-k metal oxide layer 114 at the interface of layer 112. Choi 50-52.
As the Examiner explains (Ans. 5), the oxidizing agent will react with the
ZrCf or A1NX at the interface of layer 112 to form a high-k oxide material
Zr02 or AlOx between the semiconductor substrate (100 + 110) and the layer
of high-k oxide material 114. See, e.g., Choi 158 (disclosing that the “high-
k dielectric layer may include a zirconium oxide layer (ZrOx)”); see also
Choi, Fig. 3.
Appellant’s arguments do not reveal reversible error in the
Examiner’s factual findings and analysis in this regard.
Appellant’s assertions at page 7 of the Appeal Brief that Choi does not
disclose the first and second depositing steps of claim 1 are not persuasive of
reversible error because they are conclusory and Appellant does not provide
an adequate technical explanation to support them. Attorney argument is not
evidence. In re De Blauwe, 736 F.2d 699, 705 (Fed. Cir. 1984).
Appellant’s assertions that “[o]ne of ordinary skill in the art would
readily know that dielectric materials are insulators, whereas metals [in]
non-oxidized state are conductors” (App. Br. 6) and the step of depositing a
first dielectric layer 112 disclosed in Choi is “not the same” as the first
depositing step of claim 1 (id. at 7) are also conclusory and thus, equally
unpersuasive of reversible error in the Examiner’s rejection. De Blauwe,
736 F.2d at 705; cf. also In re Lovin, 652 F.3d 1349, 1356-57 (Fed. Cir.
2011) (holding that a “naked assertion” that the references fail to disclose or
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Application 14/718,125
suggest a claim limitation is not an argument in support of separate
patentability).
In the Reply Brief, Appellant raises several new arguments that
Appellant did not previously raise in the Appeal Brief. See Reply Br. 2—5.
First, Appellant argues that the Examiner’s rejection should be
reversed because:
the ordinary customary meaning of the claimed term
“metal” as it would be read by one of ordinary skill in the
art at the time of the invention would not include metal
chloride compounds such as ZrCl4 or metal nitride
compounds such as A1NX.
Reply Br. 3. In particular, Appellant contends that because the Specification
lists only “elemental metals as choices” for the term metal, “one of ordinary
skill in the art would not consider depositing the chloride compound ZrCf
or the nitride compound A1NX as being equivalent to the claimed step of
‘depositing a layer of metal. . . wherein the layer of metal is deposited in a
non-oxidized state.’” Id. at 3 (citing Spec. 19).
Next, Appellant argues that the rejection should be reversed because
Choi does not disclose “depositing a layer of metal on the semiconductor
surface,” as required by claim 1. Reply Br. 3 (emphasis added). In
particular, Appellant contends that Figure 1 of Choi “shows Choi’s second
dielectric layer 114 on top of the first dielectric layer 112 which is provided
on top of the electrode 110 instead of being deposited ‘on the semiconductor
surface’ as recited in Claim 1.” Id. at 4.
Appellant further contends that:
it would have been apparent to one of ordinary skill in
the art that Choi’s first electrode 110 is a separate
intervening layer such that Choi’s first dielectric layer
112 would not be considered to be ‘deposited] ... on the
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semiconductor surface’ (i.e., it is not deposited on the
surface of Choi’s substrate 100) as recited in Claim 1.
Reply Br. 5.
Appellant does not explain why these arguments were not raised in
the Appeal Brief. See generally Reply Br. 1—5. We, therefore, decline to
consider them.4 “The reply brief is not an opportunity to make arguments
that could have been made during prosecution, but were not. Nor is the
reply brief an opportunity to make arguments that could have been made in
the principal brief on appeal to rebut the Examiner’s rejections, but were
not.” Ex parte Borden, 93 USPQ2d 1473, 1474 (BPAI 2010) (Informative);
see also Cross Med. Prods., Inc. v. Medtronic Sofamor Danek, Inc., 424
F.3d 1293, 1320—21 n.3 (Fed. Cir. 2005) (stating that arguments not raised
in the opening brief are deemed waived); 37 C.F.R. § 41.41(b)(2).
Claims 6, 7, and 10—12
Appellant argues claims 6, 7, and 10-12 as a group. App. Br. 8. We
select independent claim 6 as representative and dependent claims 7 and 10-
12 stand or fall with claim 6. 37 C.F.R. § 41.37(c)(l)(iv).
Claim 6 is similar to claim 1 and recites the following:
A method of fabricating oxide/semiconductor
interface comprising:
receiving a non-planar semiconductor substrate
structure having a surface;
depositing a layer of metal on the non-planar
semiconductor substrate surface, wherein the layer of
metal is deposited in a non-oxidized state; and
4 We, however, take no position regarding the merits of these arguments.
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depositing a layer of high-k oxide material on the
layer of metal by an atomic layer deposition process,
whereby the layer of metal oxidizes from exposure to the
atomic layer deposition process’ oxidizing agents O3 and
H20 during the deposition of the high-k oxide material,
thus forming a high-k metal oxide layer at an interface
between the semiconductor substrate and the layer of
high-k oxide material and prevents formation of
undesirable low-k oxide interfacial layer.
Claims App’x (App. Br. 10—11) (key disputed claim language italicized and
bolded).
The Examiner determines that Choi discloses all of the steps of claim
6 and thus, anticipates the claim. Final Act. 4 (citing Choi, Figs. 5 A—5F, ||
42, 79,81,82).
Relying on principally the same argument previously presented in
response to the Examiner’s Rejection 1 regarding claim 1, Appellant
contends that the Examiner’s rejection of claim 6 should be reversed because
Choi’s dielectric layer 262 is not a metal in a “non-oxidized state” and thus,
the reference does not disclose the “depositing a layer of metal on the non-
planar semiconductor substrate surface, wherein the layer of metal is
deposited in a non-oxidized state” step, as recited in the claim. App. Br. 8.
We do not find Appellant’s argument persuasive of reversible error in
the Examiner’s rejection for principally the same reasons previously
discussed above in affirming the Examiner’s rejection of claim 1, and based
on the fact finding and well-stated reasoning provided by the Examiner at
page 6 of the Answer and page 4 of the Final Office Action.
In particular, we find that a preponderance of the evidence supports
the Examiner’s determination that Choi discloses all of the steps of claim 6,
including “depositing a layer of metal on the non-planar semiconductor
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substrate surface, wherein the layer of metal is deposited in a non-oxidized
state,” and thus, the reference anticipates the claim. Choi, Figs. 5A—5F, ||
42, 79,81,82.
Accordingly, we affirm the Examiner’s rejection of claims 1—7 and
10-12 under 35 U.S.C. § 102(b) as being anticipated by Choi.
Rejections 2 and 3
Appellant does not present any additional substantive arguments in
response to the Examiner’s Rejections 2 and 3, stated above. See App. Br. 8
(asserting that “because Claim 6 is patentable over Choi.... Claim 6 is also
allowable over the combination of Choi and Saitoh and claims 8-9 are also
allowable over the combination of Choi and Saitoh by virtue of their
dependencies”); id. at 9 (asserting that “because claims 1 and 6 are
patentable over Choi, claims 1 and 6 are also allowable over the combination
of Choi and Chen” and “claims 18 and 19 are also allowable over the
combination of Choi and Chen by virtue of their dependencies”).
Accordingly, based on the findings and technical reasoning provided
by the Examiner and for principally the same reasons discussed above for
affirming Rejection 1, we affirm the Examiner’s Rejections 2 and 3.
DECISION/ORDER
The Examiner’s rejections of claims 1—12, 18, and 19 are affirmed.
It is ordered that the Examiner’s decision is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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