Ex Parte Veal et al

Patent Trial and Appeal Board

Feb 8, 2017

13681706 (P.T.A.B. Feb. 8, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/681,706 11/20/2012 Bryan E. Veal ITL.2227C1US (P32665C) 5281
47795 7590 02/10/2017
TROP, PRUNER & HU, P.C.
1616 S. VOSS RD., SUITE 750
HOUSTON, TX 77057-2631
EXAMINER
HUYNH, KIM T
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
02/10/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
tphpto@tphm.com
Inteldocs_docketing @ cpaglobal.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BRYAN E. VEAL and ANNIE FOONG
Appeal 2016-002444
Application 13/681,7061
Technology Center 2100
Before LARRY J. HUME, TERRENCE W. McMILLIN, and
NATHAN A. ENGELS, Administrative Patent Judges.
HUME, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 1—15. The Examiner indicates claims 16—20 are
allowable. Ans. 5. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.
1 According to Appellants, the real party in interest is Intel Corp. App.
Br. 3.
Appeal 2016-002444
Application 13/681,706
STATEMENT OF THE CASE2
The Invention
Embodiments of Appellants' disclosed invention relate to source core
interrupt steering. Title.
Exemplary Claims
Claims 1 and 6, reproduced below, are representative of the subject
matter on appeal (emphases added to contested limitations):
1. At least one non-transitory machine readable
medium comprising instructions that when executed on a
computing device cause the computing device to perform a
method comprising:
receiving a core identifier that corresponds with a source
core that is included in a processor;
receiving an input/output request, produced and
originating from the source core, that is associated with the
core identifier;
storing the core identifier in a memory coupled to the
processor;
directing an interrupt, which corresponds to the request,
to the source core based on the core identifier;
wherein the processor is coupled to an additional core
and the request includes the core identifier.
6. At least one non-transitory machine readable
medium comprising instructions that when executed on a
2 Our Decision relies upon Appellants' Appeal Brief ("App. Br.," filed
Feb. 17, 2015); Reply Brief ("Reply Br.," filed July 6, 2015); Examiner's
Answer ("Ans.," mailed Apr. 23, 2015); Final Office Action ("Final Act.,"
mailed Apr. 14, 2014); and the original Specification ("Spec.," filed
Nov. 20, 2012).
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Application 13/681,706
computing device cause the computing device to perform a
method comprising:
receiving an input/output request, produced and
originating from a source core, which includes a message-
signaled interrupt (MSI) message that corresponds to one of a
source core and an additional core; and
directing an interrupt, which corresponds to the request
and the MSI message, to the one of the source core and the
additional core based on the MSI message;
wherein the source core and the additional core are
included in a processor.
Prior Art
The Examiner relies upon the following prior art as evidence in
rejecting the claims on appeal:
Wolfe US 2010/0274941 A1 Oct. 28,2010
Rejection on AppeaP
Claims 1—15 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Wolfe. Final Act. 6; Ans. 2.
3 The obviousness-type double patenting rejection of claims 1—20 over
claims 1—18 of U.S. Patent No. 8,321,615 B2 has been withdrawn by the
Examiner in response to the filing and acceptance of a Terminal Disclaimer,
such that claims 16—20 are now indicated as being allowable. Ans. 5.
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Application 13/681,706
ISSUE
Appellants argue (App. Br. 10—11; Reply Br. 1—2) the Examiner's
rejection of claim 1 under 35 U.S.C. § 102(e) as being anticipated by Wolfe
is in error. These contentions present us with the following issue:
Did the Examiner err in finding the cited prior art discloses:
(1) a non-transitory machine readable medium containing
instructions which, when executed by a computing device,
perform a method that includes, inter alia, the steps of
"receiving an input/output request, produced and originating
from the source core . . . [and] directing an interrupt, which
corresponds to the request, to the source core,"
as recited in claim 1, and
(2) a non-transitory machine readable medium containing
instructions which, when executed by a computing device,
perform a method that includes, inter alia, the steps of
"receiving an input/output request, produced and originating
from a source core, which includes a message-signaled interrupt
(MSI) message . . . [and] directing an interrupt, which
corresponds to the [input/output] request and the MSI message,
to the one of the source core and the additional core . . .,"
as recited in claim 6?
ANALYSIS
We agree with particular arguments advanced by Appellants with
respect to claims 1 and 6 for the specific reasons discussed below. We
highlight and address specific findings and arguments regarding claims 1
and 6 for emphasis as follows.
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Claim 1
"Receiving" Limitation
Appellants first argue, "Wolfe does not suggest the target I/O request
is 'FROM' a source core but instead teaches element 410a is transmitted 'TO'
a core," contrary to the recitations of claim 1. App. Br. 10 (emphasis
omitted). With respect to Wolfe Figure 4 and paragraphs 43 through 45, set
forth by the Examiner as disclosing the contested "receiving" limitation,
Appellants contend "Wolfe paints a picture whereby an interrupt is received
. . . [by a core or cores]," but "the message does not come from the cores—it
goes TO the cores," and "'core response message 420'. . . [is] sent FROM
the cores." Id.
Claim 1 of the present application includes "receiving an
input/output request, produced AND originating. FROM the
source core, that is associated with the core identifier". The OA
equates the "input/output request" of claim 1 to Wolfe item
410a. See OA, p. 10 and Wolfe, Figure 4. However, in 143
Wolfe admits 410a is "transmitted FROM . . . controller 220 . . .
TO multiple processor cores." If 410a goes from the controller
to the cores, how can it satisfy claim 1 's "input/output request,
produced and originating FROM the source core”? It cannot
and claim 1 should be allowed.
App. Br. 11. We are persuaded the Examiner erred in finding Wolfe
discloses this contested limitation because, on this record, and upon our
reading of the cited prior art, Wolfe does not disclose "receiving an
input/output request, produced and originating from the source core,” as
recited in claim 1. (Emphasis added).
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Application 13/681,706
"Directing" Limitation
Appellants argue:
Claim 1 also includes "directing an interrupt, which
corresponds to the request to the source core based on the core
identifier". The OA equates the "interrupt" of claim 1 to Wolfe
item 410b and further equates the "request" of claim 1 to Wolfe
item 410a. See OA, 10 and Wolfe, Figure 4. However, in 143
Wolfe admits 410b is an "alternative" message form to message
410a. In other words, use of 410a is an alternative embodiment
to 410b. 410a provides for a single preferred core ID while
410b instead allows for an entire list of core IDs. If these are
both just "interrupt messages" that are alternatives to one
another, how can "interrupt" 410b "correspond to the request"
(as required by claim 1) where the OA identifies the "request"
as 410a? Put another way, the OA is saying 410B (the alleged
"interrupt" of claim l) "corresponds" to 410A (the alleged
"request" of claim 1) when in fact they are alternative
embodiments to one another. Thus, the rejection of claim 1
should be withdrawn.
Id.
As indicated by Appellants, the Examiner cites Wolfe paragraphs 43
through 51 as allegedly disclosing this "directing" limitation. Final Act. 6.
In particular, Appellants allege error in the Examiner's finding that "message
410A used to indicate that an interrupt has arrived from one of the interrupt
lines to the interrupt controller is equivalent as Applicant's recited input/
output request," and "interrupt message 410B is equivalent as Applicants]
recited interrupt. Thus, the prior art teaches the invention as claimed and the
claims do not distinguish over the prior art as applied." Final Act. 10.
Appellants respond by arguing, Wolfe does not disclose the recited
"directing" step "because elements 410A and 410b are both the same type of
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messages" and are not input/output requests or interrupts. App. Br. 11
(emphasis omitted).
We agree with Appellants and find Wolfe paragraph 43 and Figure 4
disclose messages 410A and 41 OB are "example[s] of a message that may be
transmitted from an interrupt controller 220 over an interrupt bus 215 to
multiple processor cores 210. The interrupt message 410A may be used to
indicate that an interrupt has arrived from one of the interrupt lines 225 to
the interrupt controller 220." Wolfe 143. "Alternatively, a second interrupt
message 410B may indicate core affinity by providing an ordered list of core
IDs to indicate an ordered preference of processor cores 210 for handling the
pending interrupt." Id. (emphasis added). We find these two messages,
410A and 410B, cited by the Examiner, do not disclose both a "request" and
an "interrupt" responsive to the request, as claimed.
Under § 102, the prior art reference "must not only disclose all
elements of the claim within the four comers of the document, but must also
disclose those elements arranged as in the claim." Net Money IN, Inc. v.
VeriSign, Inc., 545 F.3d 1359, 1369 (Fed. Cir. 2008) (internal citation and
internal quotation marks omitted). "Thus, it is not enough that the prior art
reference discloses part of the claimed invention, which an ordinary artisan
might supplement to make the whole, or that it includes multiple, distinct
teachings that the artisan might somehow combine to achieve the claimed
invention." Id. at 1371.
In the Answer, we find the Examiner did not adequately explain the
mapping of the recited claim limitation to the prior art in a manner sufficient
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to satisfy an anticipation rejection under § 102. Ans. 6.4 Thus, we agree
with Appellants' argument that Wolfe does not disclose the recited "directing
an interrupt, which corresponds to the request, to the source core."
Accordingly, based upon the findings above, on this record, we are
persuaded of error in the Examiner's reliance on the disclosure of the cited
prior art to disclose the disputed limitation of claim 1, such that we cannot
sustain the Examiner's finding of anticipation of independent claim 1 and
dependent claims 2—5 which stand therewith.
Claim 6
Similar to the rejection of claim 1, Appellants contend Wolfe does not
disclose commensurate "receiving" and "directing" steps, as recited in
claim 6. For essentially the same reasons argued by Appellants, supra, we
disagree with the Examiner's findings. Ans. 5—6.
4 For example, the Examiner states:
As Wolfe notes at (paragraph 31-32 and 35, i.e., core response
message which corresponds to the request, since the message
that originates from the cores and includes the core ID. In
addition, As Wolfe notes at (paragraph 44, Examiner further
cited for clarification), the core response message indicate that
an individual processor core accepts control of the pending
interrupt by requesting assignment of the interrupt from the
interrupt request arbiter, wherein the core response message
include a source core ID identifying the specific processor core
from which the response originates. This is equivalent as
Appellant’s recited claims. Thus, the prior art teaches the
invention as claimed and the claims do not distinguish over the
prior art as applied.
Ans. 6 (emphasis added). Under § 102, we find the Examiner does not
adequately explain the "equivalence" of these concepts.
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Claim 6 further recites "an input/output request. . . which includes a
message-signaled interrupt (MSI) message." Appellants argue,
"[specifically, the OA states the 'request' of claim 6 and the MSI message of
claim 6 are 'equivalent.... This renders the term 'MSI message' superfluous
in claim 6." App. Br. 13.5
Appellants contend:
The specification at paragraph 17 provides "MSI is a feature
that enables a device function to request service by writing a
system-specified data value to a system-specified address using,
for example, a Peripheral Components Interconnect (PCI)
double word (DWORD) memory write transaction. The address
specifies the message destination and the data specifies the
message." Paragraph 17 further provides "MSI and MSI-X are
described in PCI Local Bus Specification, Rev. 3.0." In other
words, an MSI message is a term known to [a person of
ordinary skill in the art].
Reply Br. 2 (emphasis added); and see App. Br. 8 (Summary of Claimed
Subject Matter) (citing Spec. Tflf 28—33).
The Examiner finds:
With respect to claims 6 and 3, Appellants] argue[] that
OA does renders [sic] term "message-signaled interrupt (]MSI)
message" superfluous. Examiner respectfully disagrees. As
Wolfe notes at (paragraph 16-18), instructions and data
associated with operations on the multiple cores of the
5 Appellants argue: "Again, the OA states the 'request' of claim 6 (and claim
1) and the MSI message of claim 6 (and claim 3) are "equivalent." OA, p.
11 .In this case, it appears the OA is using the same element in Wolfe
(message 410a) to satisfy both the "receiving” element of claim 1 and the
"directing" element of claim 3, yet never explains how this single message in
Wolfe is both received from a source AND directed to the source core, and
thus no 35 U.S.C. § 102(e) prima facie case has been made." App. Br. 13—
14. We agree with Appellants' argument.
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Application 13/681,706
multiprocessor 110 may be stored on the a storage media device
for execution, software 132 associated with the multiprocessor
110 include modules[ Qi.e., interrupt service routing(ISR) or an
interrupt handler 134) for responding to interrupt events. This is
equivalent as Appellant[s] recited claims. Thus, the prior art
teaches the invention as claimed and the claims do not
distinguish over the prior art as applied.
Ans. 7 (emphasis added).
We disagree with the Examiner's finding that Wolfe's disclosure "is
equivalent as Appellants'] recited claims." We disagree because, on this
record, there is no disclosure of an MSI message in Wolfe.6
Accordingly, based upon the findings above, on this record, we are
persuaded of error in the Examiner's reliance on the disclosure of the cited
prior art to disclose the disputed limitation of claim 6, such that we cannot
sustain the Examiner's finding of anticipation of independent claim 6 and
dependent claims 7—15 which stand therewith.
CONCLUSION
The Examiner erred with respect to the anticipation rejection of
claims 1—15 under 35 U.S.C. § 102(e) over the cited prior art of record, and
we do not sustain the rejection.
DECISION
We reverse the Examiner's decision rejecting claims 1—15.
REVERSED
6 As discussed in Appellants' Specification, we find MSI to be an art-
recognized term. "MSI and MSI-X are described in PCI Local Bus
Specification, Rev. 3.0. MSI and MSI-X each allow a device to have
multiple interrupt vectors." Spec. 5.
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