Ex Parte Vaidyanathan et al

Patent Trials and Appeals Board

Feb 5, 2016

12137683 - (D) (P.T.A.B. Feb. 5, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/137,683 06/12/2008
35525 7590 02/09/2016
IBM CORP (YA)
C/O YEE & AS SOCIA TES PC
P.O. BOX 802333
DALLAS, TX 75380
FIRST NAMED INVENTOR
Basu Vaidyanathan
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
A US9200709llUS1 8021
EXAMINER
COYER, RY AND
ART UNIT PAPER NUMBER
2197
NOTIFICATION DATE DELIVERY MODE
02/09/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ptonotifs@yeeiplaw.com
mgamez@yeeiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BASU VAIDYANATHAN, KA VANA NANDIKUR BHAT, and
NITINKUMAR
Appeal2014-004142
Application 12/137,683
Technology Center 2100
Before BRUCE R. WINSOR, LINZY T. McCARTNEY, and
NATHAN A. ENGELS, Administrative Patent Judges.
ENGELS, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from the final rejection
of claims 1---6 and 8-20. We have jurisdiction under 35 U.S.C. § 6(b ).
Claim 7 is canceled. See Final Act. 2; Br. 22.
We affirm-in-part.
STATEMENT OF THE CASE
The Claims
Claim 1 of Appellants' invention is independent and illustrative of the
subject matter on appeal:
1 According to Appellants, the real party in interest is International Business
Machines Corporation. Br. 2.
Appeal2014-004142
Application 12/137,683
1. A computer program product compnsmg a computer
readable storage medium containing a plurality of instructions
encoded thereon, the plurality of instructions being executable to
cause a computing device to perform steps comprising:
setting a breakpoint within a load-store sequence;
determining if the breakpoint will cause the load-store
sequence to repeatedly fail; and
generating a warning if it is determined that the breakpoint
will cause the load-store sequence to repeatedly fail.
Br. 21.
The Examiners Rejections
Claims 1---6 and 8 stand rejected under 35 U.S.C. § 101 as directed to
non-statutory subject matter. See Final Act. 2.
Claims 1-5, 8-12, and 15-20 stand rejected under 35 U.S.C. § 102(b)
as anticipated by Alverson et al. (US 6,848,097 B 1; published Jan. 25, 2005)
("Alverson"). See Final Act. 3-12.
Claims 6; 13; and 14 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Alverson and Lev et al. (US 2008/0005193 Al; published
Jan. 3, 2008) ("Lev"). See Final Act. 12-15.
ANALYSIS
REJECTION UNDER 35 U.S.C. § 101
Claim 1 includes the limitation "a computer program product
comprising a computer readable storage medium." Appellants argue one
skilled in the art would not construe a computer readable storage medium as
being the same as a transmission medium because the well-known storage
capability of a computer readable storage medium is a non-transitory
capability. Br. 7-8. Citing binding precedent from the Board, the Examiner
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Application 12/137,683
concludes, and we agree, that the broadest reasonable interpretation of the
"computer readable storage medium" includes non-statutory subject matter
such as transitory signals. Ans. 16-17 (citing Ex parte Mewherter, 107
USPQ2d 1857, 1863 (PTAB 2013) (precedential)); see also David J.
Kappos, Subject Matter Eligibility of Computer Readable Media, 1351 Off.
Gaz. Pat. Office 212 (Feb. 23, 2010). We find nothing in Appellants'
Specification that effectively limits the scope of claim 1 to statutory subject
matter, and, contrary to Appellants' arguments, adding the word "storage" to
"computer readable media" claim limitations also does not exclude
transitory signals. Mewherter, 107 USPQ2d at 1863; see also Spec. i-f 25.
Accordingly, we sustain the Examiner's rejection of claims 1---6 and 8 under
35 U.S.C. § 101. See In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir.
2007).
REJECTION UNDER 35 U.S.C. § 102(b)
Appellants argue Alverson's disclosure that "[i]f the trap for the data
blocked exception is enabled, then a trap occurs" does not disclose setting a
breakpoint as recited in claim 1. Br. 11 (quoting Alverson col. 4, 11. 22-24).
Appellants also argue Alverson does not set a breakpoint "within a load-
store sequence" because it sets state bits on a specific memory location, not
within a particular sequence of instructions. Br. 11.
We find Appellants' arguments unpersuasive. As noted by the
Examiner, Appellants' Specification states that "[b]reakpoints will stop the
execution of a program so that the developer may determine if the program
is operating properly." Spec. i-f 7. Applying a broad but reasonable
interpretation in light of Appellants' Specification, the Examiner finds, and
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Application 12/137,683
we agree, that Alverson discloses the claimed "breakpoints" with its
disclosure of traps that stop execution of a program when a data-blocked
exception has been raised. Ans. 19 (citing Alverson col. 4, 11. 22-29);
accord Alverson col. 6, 11. 25-29 ("breakpoints are often implemented by
replacing an instruction in the target code with a breakpoint instruction to
halt execution of the target code (e.g., a trap instruction or a jump to the
debugger)").
We also agree with the Examiner that Alverson discloses traps "set[]
... within a load-store sequence," which Appellants' Specification defines
as "[t]he sequence of loading and then storing data." Spec. i-f 5. Among
other things, Alverson discloses traps within a "FETCH_ADD" operation
that "loads a value from a memory location, adds a result to the retrieved
value, and stores the sum back into the memory location." Ans. 19 n.1
(citing Alverson col. 4, 11. 13-20).
Appellants further argue Alverson does not disclose "determining if
the breakpoint will cause the load-store sequence to repeatedly fail" as
recited in claim 1 "because Alverson acts after the trap occurs and not before
as claimed." Br. 12. We find Appellants' argument unpersuasive and agree
with the Examiner that claim 1 encompasses predicting future failures by
detecting ongoing failures. Ans. 21. As the Examiner finds, after a failure is
detected, a determination that the failure is recurring (as taught by Alverson)
is a determination that a repeated failure will occur. See Ans. 21; Alverson
col. 4, 11. 20-29. For similar reasons, we find Appellants' argument that
Alverson does not disclose "generating a warning if it is determined that the
breakpoint will cause the load-store sequence to repeatedly fail"
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Application 12/137,683
unpersuasive and agree with the Examiner's findings. See Br. 12; Ans. 21;
Alverson col. 4, 11. 20-29. (Emphasis added).
Having considered the Examiner's rejection in view of Appellants'
arguments and the evidence of record, we find no error in the Examiner's
findings with respect to the rejection of claim 1. Accordingly, we sustain the
Examiner's rejection of independent claim 1; as well as independent claims
9 and 15 and dependent claims 2-5, 8, 10-12, and 16-20, which were not
argued separately with particularity beyond the arguments advanced for
claim 1. See Br. 12-13.
REJECTIONUNDER35 U.S.C. § 103(a)
Appellants argue neither Alverson, nor Lev, either alone or in
combination, teaches or suggests setting at least one alternate breakpoint
"outside of the load-store sequence" as recited in claim 6. Br. 15. The
Examiner finds that Lev teaches implementing an adaptive watchpoint on a
field whose location may be dynamically changed. See Lev i-fi-194--95; Ans.
24. The Examiner explains that Alverson's
load-store sequence is a set of load and store instructions []
grouped according to a common memory location, and a
breakpoint set within the sequence necessarily is associated with
that single memory location. Therefore, setting an alternative
breakpoint location, as in Lev, would in combination with
Alverson yield an alternative breakpoint location that is not
within the initial load-store sequence.
Ans. 24.
We find the Examiner erred by failing to adequately show that the
combination of Alverson and Lev teaches or suggests the disputed
limitation. See Ans. 24. More specifically, the Examiner has not adequately
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Application 12/137,683
shown how changing the location of Lev's adaptive watchpoint field teaches
or suggests "setting at least one alternate breakpoint outside of the load-store
sequence." We are unable to find, nor does the Examiner cite, any passages
in Lev that teach or suggest a different memory location causing an alternate
watchpoint to be set outside an initial watchpoint's load-store sequence. Nor
are we able to find in the evidence of record that a load-store sequence of
instructions is limited to a single memory location.
For these reasons, we are constrained by the record before us to
reverse the rejection of claim 6 under 35 U.S.C. § 103, as well as dependent
claims 13 and 14, each of which recite a similar limitation. Br. 17, 19.
DECISION
The decisions of the Examiner to reject claims 1---6 and 8 under
35 U.S.C. § 101 and claims 1-5, 8-12, and 15-20 under 35 U.S.C. § 102(b)
are affirmed.
The decision of the Examiner to reject claims 6, 13, and 14 under
35 U.S.C. § 103(a) is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l ).
See 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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