Ex Parte Vaglica

Board of Patent Appeals and Interferences

Jul 31, 2008

09956300 (B.P.A.I. Jul. 31, 2008)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

JOHN VAGLICA
____________

Appeal 2008-0628
Application 09/956,3001
Technology Center 2100
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Decided: July 31, 2008
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Before JEAN R. HOMERE, JAY P. LUCAS, and STEPHEN C. SIU,
Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134 from the Examiner’s
rejection of claims 1 through 3 and 5 through 21. Claim 4 has been
canceled. We have jurisdiction under 35 U.S.C. § 6(b). We affirm.

1 Filed on Sep. 19, 2001. The real party in interest is Freescale
Semiconductor, Inc.
Appeal 2008-0628
Application 09/956,300

The Invention
Appellant invented a method and system for saving power in a data
processing system by selectively removing power from certain non-critical
elements while maintaining power to critical elements for coming out of
powerdown. (Spec. 4.) As depicted in Figure 1, the data processing system
is mounted on an integrated circuit that includes a central processing unit
(CPU) (10), a clock generator (34) for providing clock signals to the CPU,
and a power control unit (12). (Id.) The CPU (10) includes, inter alia, a
control logic (18) for asserting instructions received from the CPU, an
execution unit (20) for executing instructions received from the control
logic, and a storage device (24) for storing information regarding the current
state of the CPU prior to entering a low power mode. (Spec.4-5.) Upon
receiving a low power signal from the CPU (10), the power control unit (12)
disables the clock generator (34) connected thereto. Consequently, a power
supply voltage is maintained across a logic unit (18) and a storage device
(24) while removing the power supply voltage from the execution unit (36).
(Spec. 6-7.)

An understanding of the invention can be derived from exemplary
independent claim 1, which reads as follows:
. 1. A data processing system on an integrated circuit, comprising:
a central processing unit (CPU) for executing instructions,
including a low power mode instruction used for entering a low power
mode;
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Application 09/956,300

wherein the CPU comprises an execution unit for
executing instructions;
a logic unit for asserting a low power mode signal in
response to the CPU entering a low power mode
instruction; and
a storage device for storing information relating to a
current state of the CPU prior to executing the low
power mode instruction, wherein the information
comprises the current state of a programmer’s
model;
a clock generator for providing a clock signal to time various
functions of the CPU;
a power control unit, coupled to the logic unit, the power
control unit receiving the low power mode signal,
and in response, the power control unit for
disabling the clock generator, maintaining a power
supply voltage to the logic unit and the storage
device, while removing the power supply voltage
from the execution unit;
wherein the central processing unit, the clock generator, and the
power control unit are on the integrated circuit.

In rejecting the claims on appeal, the Examiner relied upon the
following prior art:
Smith US 5,167,024 Nov. 24, 1992
Moyer US 5,689,714 Nov. 18, 1997
Atkinson US 6,546,472 B2 Apr. 8, 2003

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Application 09/956,300

The Examiner rejected the claims on appeal as follows:
Claims 1 through 3 and 5 through 21 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over the combination of Smith, Atkinson and Moyer.

FINDINGS OF FACT
The following findings of fact (FF) are supported by a preponderance
of the evidence.
Smith
1. Smith discloses a power manager within a laptop computer that
monitors various circuits in the laptop computer, and disconnects them when
they are not in use in order to conserve battery power. (Col. 3, ll. 33-36.)
2. As depicted in Figure 1, the portable computer (10) includes, inter
alia, a CPU (12), a power manager (11), a power control unit (27), a clock
generator (16), a storage device (RAM) (14), various registers and drivers.
(Col. 4, ll. 20-43.)
3. Upon receiving a sleep command from the CPU (12), the power
manager (11) begins the process to cause the computer to operate in sleep
mode to conserve power. (Col. 7, ll. 42-54.)
4. Before entering the sleep mode, the operating system and various
drivers of the computer save in the RAM current state information of the
computer, including the state of the registers, drivers, and other memory
devices. (Col. 7, ll. 55-59.)
5. Once the current computer states are stored in the RAM, the power
manager releases all of the switches in interface unit (26), causing power to
be removed from various units of the computer. (Col. 7, ll. 59-65.)
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6. Alternatively, upon receiving the sleep mode command from the
CPU (12), the power manager (11) disables the clock input of clock control
unit (27) to the CPU to thereby halt the execution of the CPU while the
internal RAM and control registers of the CPU remain intact. (Col. 8, ll. 7-
16.)
Atkinson
7. Atkinson discloses a computer system that supports a fast
hibernation mode of operation in order to save power. Particularly, Atkinson
discloses manipulating data stored in RAM when the computer is placed in
low power mode to minimize latency. (Col. 1, ll. 15-21.) The system
includes hardware that monitors units of the computer such as the memory
controller, and the CPU to detect when data in memory has changed. (Col. 4,
ll. 38-41.)

Moyer
8. Moyer discloses a low power management data processing system
(10) having a CPU that communicates low power control status values to a
register file within the processor. (Abstract.)

PRINCIPLES OF LAW
Appellants have the burden on appeal to the Board to demonstrate
error in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86
(Fed. Cir. 2006) (“On appeal to the Board, an applicant can overcome a
rejection [under § 103] by showing insufficient evidence of prima facie
obviousness or by rebutting the prima facie case with evidence of secondary
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indicia of nonobviousness.”) (quoting In re Rouffet, 149 F.3d 1350, 1355
(Fed. Cir. 1998)).
The Supreme Court in Graham v. John Deere Co., 383 U.S. 1, 17-18
(1966), stated that the following factual inquiries underpin any
determination of obviousness:
Under § 103, [1] the scope and content of the prior art are to be
determined; [2] differences between the prior art and the claims
at issue are to be ascertained; and [3] the level of ordinary skill
in the pertinent art resolved. Against this background, the
obviousness or nonobviousness of the subject matter is
determined. Such (4) secondary considerations as commercial
success, long felt but unsolved needs, failure of others, etc.,
might be utilized to give light to the circumstances surrounding
the origin of the subject matter sought to be patented. As
indicia of obviousness or nonobviousness, these inquiries may
have relevancy.

Where the claimed subject matter involves more than the simple
substitution of one known element for another or the mere application of a
known technique to a piece of prior art ready for the improvement, a holding
of obviousness must be based on “an apparent reason to combine the known
elements in the fashion claimed.” KSR Int’l v. Teleflex, Inc., 127 S. Ct.
1727, 1740-41 (2007). That is, “there must be some articulated reasoning
with some rational underpinning to support the legal conclusion of
obviousness.” Id., 127 S. Ct. at 1741 (quoting In re Kahn, 441 F.3d 977,
988 (Fed. Cir. 2006)). Such reasoning can be based on interrelated teachings
of multiple patents, the effects of demands known to the design community
or present in the marketplace, and the background knowledge possessed by a
person having ordinary skill in the art. KSR, 127 S. Ct. at 1740-41.
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ANALYSIS
Independent claims 1, 12, and 21 recite in relevant part in response to
receiving a low power mode signal from a CPU, a power control unit
disables a clock generator to maintain power to a logic unit and a storage
device of the CPU while removing power from the execution unit of the
CPU. (Claims Appendix.) Appellant argues that the combination of Smith,
Atkinson and Moyer does not teach those limitations. Particularly,
Appellant submits that Smith’s RAM does not store information relation to
the state of the CPU, and nor does it teach that the CPU enters a low power
mode. (App. Br. 6-7, Reply Br. 4-5.) Appellant further submits that neither
Atkinson nor Moyer remedies the deficiencies of Smith. (Id.) The
Examiner, in response, finds that Smith’s registers data stored in the RAM
prior to the CPU entering the sleep mode is part of the CPU. The Examiner
further finds that Smith discloses removing power from the various units of
the CPU, and in another embodiment, Smith teaches halting the execution of
the CPU when it is in the sleep mode. The Examiner consequently
concludes that Smith, taken in combination with Atkinson and Moyer
teaches the claimed invention. (Ans. 11-12.)
Therefore, the pivotal issue before us is whether one of ordinary skill
in the art would find that the combination of Smith, Atkinson and Moyer
teaches a RAM that stores information about the CPU status when the CPU
enters a sleep mode to thereby maintain power to the CPU, the RAM and the
logic unit while removing power to the CPU execution unit, as claimed. We
answer this inquiry in the affirmative.
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As detailed in the Findings of Facts section above, Smith discloses a
laptop computer including a CPU, a RAM, a power manager, various
registers and drivers. (FF. 2.) Smith also discloses that the RAM stores pre-
sleep mode information about the current state of the laptop computer
including registers, drivers and other memory devices. (FF. 4.) One of
ordinary skill in the art would readily recognize that, as correctly noted by
the Examiner, some of these registers, drivers and other memory devices
belong to the power manager and the CPU. Therefore, the ordinarily skilled
artisan would reasonably appreciate that Smith’s RAM also includes pre-
sleep mode information about the state of the CPU registers and memories.
Next, as set forth above, Smith discloses that the CPU sends a signal
to the power manager to enter in the sleep mode to place the computer in the
sleep mode. (FF. 3.) Further, Smith discloses that after the RAM has stored
status information about the computer, in response to the CPU command to
place the computer in the sleep mode, the power manager releases all the
switches, which causes power to be removed from various units of the
computer. (FF. 5.) The ordinarily skilled artisan would readily recognize
that by removing power from various (not all) units of the computer in the
sleep mode, Smith teaches that when the computer is placed in the sleep
mode, power is removed from some of its units while power is maintained in
others. This teaching becomes more evident in Smith’s alternative
embodiment, which explicitly indicates that in the sleep mode the CPU
disables the clock controller in order to halt the execution of the CPU while
the internal states of the CPU containing the RAM and the registers remain
intact. (FF. 6.) The ordinarily skilled artisan would readily recognize that
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Smith’s halting the execution of the CPU teaches removing power from the
execution unit when the computer is placed in the sleep mode. Similarly, the
ordinarily skilled artisan would recognize that Smith’s freezing of the CPU,
the RAM and registers teaches maintaining the power to the RAM and the
logic unit when the computer is placed in the sleep mode.
Additionally, the ordinarily skilled artisan would readily appreciate
Atkinson and Moyer’s disclosures, detailed above, reasonably complement
Smith’s teachings. The combined teachings of the cited references amount
to known elements in the art that perform their routine functions to achieve a
predictable result. More particularly, the combined teachings would
predictably result in a computer system that, upon being placed in a sleep
mode, removes power from the execution unit of its CPU while retaining
power across the RAM and logic units of the CPU. It follows that
Appellant has shown that the Examiner erred in finding that the combination
of Smith, Atkinson and Moyer renders claim 1 unpatentable.
Appellant did not provide separate arguments with respect to the
rejection of claims 2, 3, and 5 through 21. Therefore, we select independent
claim 1 as being representative of the cited claims. Consequently, these
claims fall together with representative claim 1. 37 C.F.R.
§ 41.37(c)(1)(vii).

CONCLUSION OF LAW
Appellant has not shown that the Examiner erred in concluding that
the combination of Smith, Atkinson and Moyer renders claims 1 through 3
and 5 through 21 unpatentable under 35 U.S.C. § 103(a).
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DECISION
We affirm the Examiner’s decision rejecting claims 1 through 3 and 5
through 21.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

tdl/ce

FREESCALE SEMICONDUCTOR, INC.
LAW DEPARTMENT
7700 WEST PARMER LANE MD:TX32/PL02
AUSTIN TX 78729
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