Ex Parte Ullal et al

Patent Trial and Appeal Board

Sep 26, 2017

13154061 (P.T.A.B. Sep. 26, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/154,061 06/06/2011 VijayUUal 16483.0900US01/MAXM-0900 1279
99900 7590 09/28/2017
Advent/Maxim
The Advent Building
17838 Burke Street
Suite 200
Omaha, NE 68118
EXAMINER
CHIN, EDWARD
ART UNIT PAPER NUMBER
2813
NOTIFICATION DATE DELIVERY MODE
09/28/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
u spto @ adventip .com
sloma@adventip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte VIJAY ULLAL
and ARKADII V. SAMOILOV
Appeal 2016-005786
Application 13/154,061
Technology Center 2800
Before GEORGE C. BEST, DONNA M. PRAISS, and
MICHAEL G. McMANUS, Administrative Patent Judges.
BEST, Administrative Patent Judge.
DECISION ON APPEAL
The Examiner finally rejected claims 1—8 and 10—14 of Application
13/154,061 under 35 U.S.C. § 103(a) as obvious. Final Act. (December 10,
2014). Appellants1 seek reversal of these rejections pursuant to 35 U.S.C.
§ 134(a). We have jurisdiction under 35 U.S.C. § 6.
For the reasons set forth below, we affirm-in-part.
1 Maxim Integrated Products, Inc. is identified as the real party in interest.
Appeal Br. 3.
Appeal 2016-005786
Application 13/154,061
BACKGROUND
Traditional semiconductor manufacturing processes create a plurality
of integrated circuits on a semiconductor wafer. Spec. 11. The wafer is
subsequently segmented into individual integrated circuit chips. Id. Each
chip is then assembled or packaged to form a semiconductor device that may
be mounted to a printed circuit board. Id.
The ’061 Application describes wafer-level packaging devices. Id.
12. Wafer-level packaging encompasses a variety of techniques in which
integrated circuit chips are packaged at the wafer level, i.e. before
segmentation. Id. In particular, the ’061 Application describes methods for
making wafer-level package semiconductor devices in which the smallest
distance between two adjacent attachment bumps is smaller than about 25%
of a pitch between the two adjacent attachment bumps. Id. 13. The reduced
distance between the adjacent attachment bumps is said to increase solder
reliability. Id.
Claim 1 is representative of the ’061 Application’s claims and is
reproduced below from the Claims Appendix:
1. A wafer-level package device comprising:
an integrated circuit chip; and
a plurality of reflowed attachment bumps disposed on the
integrated circuit chip,
wherein a smallest distance between two adjacent
reflowed attachment bumps of the plurality of reflowed
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Application 13/154,061
attachment bumps is smaller than twenty-five percent of a pitch
between the two adjacent reflowed attachment bumps.
Appeal Br. 19.
REJECTIONS
On appeal, the Examiner maintains the following rejections:
1. Claims 1, 3, 4, and 7 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Meyer.2 Final Act. 2.
2. Claim 2 is rejected under 35 U.S.C. § 103(a) as unpatentable over
the combination of Meyer and Hashimoto.3 Final Act. 5.
3. Claims 5, 6, 8, 10, and 12—14 are rejected under 35 U.S.C. § 103(a)
as unpatentable over the combination of Meyer and Sakaguchi.4
Final Act. 6.
4. Claim 11 is rejected under 35 U.S.C. § 103(a) as unpatentable over
the combination of Meyer, Sakaguchi, and Hashimoto. Final
Act. 9.
DISCUSSION
Appellants present specific arguments for the reversal of the rejection
of independent claims 1 and 8. See Appeal Br. 12—17. Appellants also
present a separate argument for reversal of the rejection of claim 5. See id.
at 14. The remaining dependent claims—i.e., claims 2—4, 6, 7, and 10-14—
2 US 2009/0256256 Al, published October 15, 2009.
3 US 6,583,516 B2, issued June 24, 2003.
4 US 2010/0109160 Al, published May 6, 2010.
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Application 13/154,061
are alleged to be patentable based upon their dependence from a patentable
independent claim. See id. at 14—15, 16—17.
We shall address Appellants’ arguments with respect to each of claims
1,5, and 8. Each remaining claim will stand or fall with the independent
claim from which it ultimately depends.
Claim 1. Appellants argue that the rejection of claim 1 should be
reversed because the Examiner has not established a prima facie case of
obviousness. Appeal Br. 12. In particular, Appellants argue that “the
primary reference, Meyer, fails to teach or suggest ‘wherein a smallest
distance between two adjacent reflowed attachment bumps of the
plurality of reflowed attachment bumps is smaller than twenty-five percent
of a pitch between the two adjacent reflowed attachment bumps’ as presently
recited in claim 1.” Id. at 12—13. In making this argument, Appellants
assert that the Examiner erroneously found that the distance between two
adjacent reflowed attachment bumps in the structure described in Meyer is
equal to the diameter of the reflowed attachment bumps described in Meyer.
Id. at 13 (quoting Final Act. 2—3).
Appellants’ argument does not persuade us that the Examiner
reversibly erred in rejecting claim 1. As the Examiner found, Meyer
describes an example of a wafer-level packaged integrated circuit chip in
which the smallest distance between two adjacent attachment bumps is
smaller than 30% of the pitch between the two adjacent attachment bumps.
Final Act. 2—3 (citing Meyer 128). Furthermore, the Examiner’s Answer
explains the basis for this finding in explicit detail. See Answer 2—A. The
Examiner further explained why it would have been obvious to a person
having ordinary skill at the time of the invention to reduce the distance
between adjacent solder bumps using routine experimentation to arrive at the
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Application 13/154,061
claimed ratio of the distance between adjacent solder bumps and the pitch.
Final Act. 3.
Appellants have not identified reversible error in the Examiner’s
analysis. We, therefore, affirm the rejection of claim 1 as unpatentable over
Meyer.
Claim 5. Claim 5 is reproduced below:
5. The wafer-level package device as recited in claim 1,
wherein each attachment bump of the plurality of attachment
bumps is formed about a post structure.
Appeal Br. 19 (emphasis added).
Appellants argue that
none of the cited references, either alone or in combination,
teach or suggest where each attachment bump of the plurality of
attachment bumps is formed about a post structure, as recited in
dependent claim 5 (FIG. 3 illustrates an embodiment of this
structure). Instead, the Office Action merely asserts, without
evidence, that each attachment bump recited by Sakaguchi can
be interpreted as being formed “about a post structure 20/20a.”
See Final Office Action, page 6. Instead, the device in
Sakaguchi actually discloses an “insulating dam layer 20” and
an “opening portion 20a,” which is not an attachment bump
formed about a post as recited in claim 5. In fact, Sakaguchi
nowhere teaches a post structure. The other dependent claims
in the current application are similarly rejected without
objective evidence.
Id. at 14.
We begin by considering the proper interpretation of the claim term
“about.” See In re Paulsen, 30 F.3d 1475, 1479 (Fed. Cir. 1994) (“[T]o
properly compare [the prior art] with the claims at issue, we must construe
the term [in dispute] to ascertain its scope and meaning.”). During
prosecution, the PTO gives the language of the proposed claims the broadest
reasonable meaning of the words in their ordinary usage as they would be
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Application 13/154,061
understood by one of ordinary skill in the art, taking into account any
definitions or other enlightenment provided by the written description
contained in the applicant’s specification. In re Morris, 127 F.3d 1048,
1054—55 (Fed. Cir. 1997).
In this case, we conclude that the broadest reasonable interpretation of
the term “about” is “around.” We base this interpretation upon our review
of the ’061 Application’s Specification, especially 121 and Figure 3.
Based upon our interpretation, we determine that the Examiner
reversibly erred by finding that Sakaguchi describes or suggests forming a
reflowed solder bump about a post. We, therefore, reverse the rejection of
claim 5.
Claim 8. Appellants’ argument for reversal of the rejection of
independent claim 8 is substantially identical to the argument presented with
respect to independent claim 1. Compare Appeal Br. 15—16 with Appeal Br.
12—14. As discussed above, Appellants have not demonstrated reversible
error in the Examiner’s rejection. Thus, we also affirm the rejection of claim
8.
CONCLUSION
For the reasons set forth above, we affirm the rejection of claims 1—4,
6—8, and 10—14 of the ’061 Application. We, however, reverse the rejection
of claim 5.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED-IN-PART
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