Ex Parte UenoDownload PDFBoard of Patent Appeals and InterferencesNov 8, 201111723819 (B.P.A.I. Nov. 8, 2011) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/723,819 03/22/2007 Yosuke Ueno SON-3729 8098 23353 7590 11/08/2011 RADER FISHMAN & GRAUER PLLC LION BUILDING 1233 20TH STREET N.W., SUITE 501 WASHINGTON, DC 20036 EXAMINER GANNON, LEVI ART UNIT PAPER NUMBER 2817 MAIL DATE DELIVERY MODE 11/08/2011 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE _____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES _____________ Ex parte YOSUKE UENO _____________ Appeal 2010-004362 Application 11/723,819 Technology Center 2800 ______________ Before ALLEN R. MacDONALD, ROBERT E. NAPPI, and MICHAEL R. ZECHER, Administrative Patent Judges. NAPPI, Administrative Patent Judge. DECISION ON APPEAL Appeal 2010-004362 Application 11/723,819 2 This is a decision on appeal under 35 U.S.C. § 134(a) of the rejection of claims 1 through 8. We affirm-in-part. INVENTION The invention is directed a ring voltage controlled oscillator. See Specification pages 8, 9, figures 1 and 4A. Claim 1 is representative of the invention and reproduced below: An oscillating circuit comprising: N (N denotes even numbers of four or more) nodes configured to output oscillating signals having respective different phases; a main loop circuit including N inverting circuits cascaded in a form of a ring via said N nodes; and a plurality of auxiliary loop circuits each including even numbers of inverting circuits cascaded in a form of a ring, wherein each inverting circuit in said auxiliary loop circuits is connected in parallel with even numbers of inverting circuits cascaded in said main loop circuit, circuits configured to feed back signals from outputs to inputs of the respective inverters of said main loop circuit have circuit configurations equivalent to each other, and each inverting circuit in said main loop circuit and said auxiliary loop circuits drives an output line such that a phase of an output signal is inverted with respect to a phase of an input signal and has driving power that becomes lower when the phases of the output signal and the input signal are inverted with respect to each other than when the output signal and the input signal are in phase with each other. Appeal 2010-004362 Application 11/723,819 3 REFERENCE LIU US 7,338,817 B2 Mar. 4, 2008 Lizhong Sun & Tadeusz A. Kwasniewski, A 1.25-GHz O.35-um Monolithic CMOS PLL Based on a Multiphase Ring Oscillator, IEEE Journal of Solid- State Circuits, Vol. 36, No.6, 910-916 (2001) (hereinafter “Sun”). REJECTIONS AT ISSUE The Examiner has rejected claims 1 and 5 under 35 U.S.C. § 102(b) as being anticipated over Sun. Answer 3-51. The Examiner has rejected claims 2 through 4, and 6 through 8 under 35 U.S.C. § 103(a) as being unpatentable over Sun in view of Liu. Answer 5-6. ISSUES Appellant argues on pages 7 and 8 of the Brief2 that the Examiner’s anticipation rejection of claims 1 and 5 is in error for four reasons. These arguments present us with the following issues: 1. Did the Examiner error finding that Sun discloses N nodes to output oscillating signals as recited in claim 1? 2. Did the Examiner error in finding that Sun teaches a circuit wherein each inverting circuit in the auxiliary loop is connected in parallel with even numbers of inverting circuits as recited in claim 1? 1 Throughout this opinion we refer to the Examiner’s Answer mailed on September 2, 2009. 2 Throughout this opinion we refer to the Appeal Brief dated June 26, 2009 and Reply Brief dated November 23, 2009. Appeal 2010-004362 Application 11/723,819 4 3. Did the Examiner error in finding that Sun teaches a circuit wherein each inverting circuit in the auxiliary loop is connected in parallel with N/2 of inverting circuits as recited in claim 5? 4. Did the Examiner error in using Liu in rejecting claims 1 and 5? With respect to the rejection of claim 2 through 4 and 6 through 8 Appellant’s arguments on page 9 through 15 of the Brief presents us with the additional issue: Did the Examiner error in finding that the combination of the references teaches a current source to hold constant a sum total of power supply currents supplied to the respective inverting circuits by a common node?3 ANALYSIS Claims 1and 5 We have reviewed the Examiner’s rejection in light of Appellant’s arguments that the Examiner has erred. We disagree with Appellant’s conclusion that the Examiner erred in finding: 1) Sun discloses N nodes to output oscillating signals; 2) the circuit wherein each inverting circuit in the auxiliary loop is connected in parallel with even numbers of inverting circuits; 3) Sun teaches the circuit wherein each inverting circuit in the auxiliary loop is connected in parallel with N/2 of inverting circuits; and 4) the Examiner erred in using Liu in rejecting claims 1 and 5. We concur with the conclusion reached by the Examiner. Accordingly, we sustain the Examiner’s rejection of claims 1 and 5. 3 We note that Appellant presents additional issues with respect to these claims, however we do not reach these issues as this issue is dispositive of the case. Appeal 2010-004362 Application 11/723,819 5 Issue 1) The Examiner has found that Sun teaches an oscillation circuit comprising 4 nodes (figure 12, main loop M1-M4) and an even number of auxiliary loop circuits (figure 12, S1-S4). Answer 3, 8. We concur with these findings as they are supported by ample evidence, we note that the arrangement of inverting circuits in the main and auxiliary loops of Appellant’s figure 4A and Sun’s figure 12 are almost identical. Appellant’s arguments in the Brief do not address the Examiner’s findings regarding figure 12 but rather address Sun’s figure 5. We recognize that Appellant, in the Reply Brief, addresses the embodiment of figure 12, and raises issues not presented in the Brief. The, Examiner’s rejection as presented in the Final Rejection dated March 9, 2009, clearly identified Sun’s embodiment of figure 12,was relied upon to reject claim 1. Thus, Appellant had notice at the time of filing of the Brief, that the rejection was based upon figure 12, as such Appellant’s arguments directed to figure 12 which were raised for the first time in the Reply Brief have not been considered as they are deemed waived. See Ex parte Borden, 93 USPQ2d 1473, 1473-74 (BPAI 2010) (“informative”4) (absent a showing of good cause, the Board is not required to address argument in Reply Brief that could have been presented in the principal Brief). Accordingly, Appellant has not persuaded us that the Examiner erred finding that Sun discloses N nodes to output oscillating signals. Appeal 2010-004362 Application 11/723,819 6 Issue 2) The Examiner has found that Sun teaches that each inverting circuit in the auxiliary loop is in parallel with even number of inverting circuits, e.g. in figure 12, S1 is in parallel with inverters M1 and M4. Answer 3, 4, 8 and 9. We concur with these findings as they are supported by ample evidence and are consistent with the teachings of Figure 12. Appellant’s arguments in the Brief do not address the Examiner’s findings regarding figure 12, but rather discuss formulas presented on page 912 of Sun’s disclosure. Accordingly, Appellant has not persuaded that the Examiner erred in finding that Sun teaches a circuit wherein each inverting circuit in the auxiliary loop is connected in parallel with even numbers of inverting circuits as recited in claim 1. Issue 3) The Examiner finds that Sun teaches the inverting circuit in the auxiliary loop is in parallel with N/2 of inverting circuits, e.g. in figure 12, N=4 so N/2=2 and as S1 is in parallel with two inverters M1 and M4. We concur with these findings as they are supported by ample evidence and are consistent with the teachings of Figure 12. As with Issue 2 above, Appellant does not address these findings by the Examiner but rather discuss a formula on page 912 of Sun’s disclosure. Accordingly, Appellant has not persuaded us that the Examiner erred in finding that Sun teaches a circuit wherein each 4 The “informative” status of this opinion is noted at the following Board website: http://www.uspto.gov/ip/boards/bpai/decisions/inform/index.jsp. Appeal 2010-004362 Application 11/723,819 7 inverting circuit in the auxiliary loop is connected in parallel with N/2 of inverting circuits as recited in claim 5. Issue 4) Appellant’s arguments on page 8 of the Brief that the rejection of claims 1 and 5 is in error because Liu does not teach the presence of a main loop circuit with auxiliary circuits are moot. The Examiner rejected claims 1 and 5 as anticipated by Sun, as such the teachings of Liu are irrelevant to the Examiner’s rejection. Claims 2 through 4 and 6 through 8 Appellant’s augments have persuaded us that the Examiner erred in finding the combination of the references teaches a current source to hold constant a sum total of power supply currents supplied to the respective inverting circuits by a common node. The Examiner finds that Sun does not teach this limitation, and combines Sun with Liu’s teaching of single current source that provides total current to the inverter circuits. Answer 5. The Examiner concludes that the skilled artisan would combine the teachings in order to provide an enabling mechanism to the inverter circuits. Answer 5, 9. Appellant argues that this does not teach the current source circuit holds constant a sum total of power supply currents supplied to the inverting circuits via the common node. Brief 14-15. We concur, while this combined teaching may teach a common node to supply current the Examiner has not shown that it holds constant a sum total of power supply currents as recited in claims 2 and 6. Claims 3, 4, 7 and 8 depend upon Appeal 2010-004362 Application 11/723,819 8 claims 2 and 6 respectively. Accordingly we will not sustain the Examiner’s rejection of claims 2 through 4 and 6 through 8. SUMMARY Appellant’s arguments directed to the rejection of claims 1 and 5 have not persuaded us of error in the Examiner’s rejection. Appellant’s arguments however have persuaded us of error in the Examiner’s rejection of claims 2 through 4 and 6 through 8. ORDER The decision of the Examiner to reject claims 1 through 8 is affirmed in part. No time period for taking any subsequent action on connection with this appeal may be extended under 37 C.F.R. 1.136(a)(1)(iv) AFFIRMED-IN-PART ke Copy with citationCopy as parenthetical citation