Ex Parte Truong et al

Board of Patent Appeals and Interferences

Sep 7, 2007

11111799 (B.P.A.I. Sep. 7, 2007)

The opinion in support of the decision being entered
today is not binding precedent of the Board.

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte HO DAI TRUONG and CHONG MING LIN
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Appeal 2007-1650
Application 11/111,7991
Technology Center 2800
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Decided: September 7, 2007
____________________

Before: ALLEN R. MACDONALD, JAY P. LUCAS and JOHN A.
JEFFERY, Administrative Patent Judges.

LUCAS, Administrative Patent Judge.

DECISION ON APPEAL

1 Application was filed on 4/22/05, the latest application in approximately
10 generations of continuations, divisionals and CIPs originally filed on
3/2/92, some applications of which have matured to patents (Specification
1). The real party in interest is Seiko Epson Corporation, of Japan.

Appeal 2007-1650
Application 11/111,799

STATEMENT OF CASE
Appellants appeal from a final rejection of claims 20, 21, 23, 26-28,
30, and 332 under authority of 35 U.S.C. § 134. The Board of Patent
Appeals and Interferences (BPAI) has jurisdiction under 35 U.S.C. § 6(b).
An Oral Hearing was held on August 7, 2007.
Appellants’ invention relates to an improved clock signal generator in
an integrated circuit in which the effective speed of the clock signals can be
controlled by either hardware changes or by post-production software
control signals. The programmability allows the manufacturer to speed up
the clock to a point just below where the clock pulses would overlap. In the
words of the Appellants:
During the manufacturing phases of chip production,
characteristics of the on-chip clock generator are altered to ensure the
edges of the two generated clocks do not overlap. This allows the
manufacturer to optimize the performance of the chip while the chip is
undergoing initial production testing. This feature obviates the need
to perform costly and time consuming trial-and-error design and
redesign of on-chip clock generators.

Additionally, the present invention provides a technique for
optimizing the performance of the on-chip clock generator after the
chips have left the manufacturing environment. One feature of the
present invention is the ability to adjust clock generation dynamically
to account for climatic changes in an operational, or other post-
production, environment. This allows chips to be manufactured with
wider tolerances and allows operation of the chip to be optimized
when the chip is in the operational environment.

(Specification 4).

2 Claims 22, 24, 25, 29, 31, and 32 were objected to, and were indicated to be
allowable if put into independent form. (Final Rejection, mailed 3/6/06,
page 4)
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Application 11/111,799

Claim 20 is exemplary:
20. A hardware-programmable clock generator for an integrated circuit
chip, comprising:
a clock input portion;
first and second clock outputs;
a first feedback path coupling the first clock output to the clock input
portion;
a second feedback path coupling the second clock output to the clock
input portion; and
a first plurality of switches coupled to the first feedback path, each of
the first plurality of switches configurable during manufacturing to couple a
corresponding one of a first plurality of delay elements in series along the
first feedback path, wherein the coupling of delay elements along the first
feedback path controls the amount of time that clock edges associated with
the first and second clock outputs are non-overlapping.

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Walters, Jr. US 5,041,738 Aug. 20, 1991
(filed Dec. 4, 1989

Rejection:
Claims 20, 21, 23, 26-28, 30, and 33 stand rejected under 35 U.S.C.
§ 102(e) for being anticipated by Walters. Claims 22, 24, 25, 29, 31, and 32
have been objected to, and have been indicated as being allowable if the
limitations of their respective independent and intermediate claims are
included in them. (Final Rejection 4, filed March 6, 2006).
Appellant contends that the claimed subject matter is not anticipated
by Walters for failure of the references to teach limitations in the claims, as
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Application 11/111,799

will be discussed more fully below. The Examiner contends that each of the
claims is properly rejected.
Rather than repeat the arguments of Appellants or the Examiner, we
make reference to the Briefs and the Answer for their respective details.
Only those arguments actually made by Appellants have been considered in
this decision. Arguments which Appellants could have made but chose not
to make in the Briefs have not been considered and are deemed to be
waived. See 37 C.F.R. § 41.37(c)(1)(vii) (2004).3

We affirm.
ISSUE
The issue is whether Appellants have shown that the Examiner erred
in rejecting the claims under 35 U.S.C. § 102(e). The issue turns on whether
all of the claimed elements are to be found in the Walters reference.

FINDINGS OF FACT
Findings with respect to the rejection of claims 20, 21, 23, 26-28, 30,
and 33 under 35 U.S.C. § 102(e).
1. Appellants have invented a circuit for the generation of clock
signals on an integrated circuit (IC). The generator accepts an

3 Appellants have not presented any substantive arguments directed
separately to the patentability of the dependent claims or related claims,
except as will be noted in this opinion. In the absence of a separate
argument with respect to those claims, they stand or fall with the
representative independent claim. See In re Young, 927 F.2d 588, 590, 18
USPQ2d 1089, 1091 (Fed. Cir. 1991).

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Application 11/111,799

input from an external system clock, and then generates two
complementary clock signals for use on the IC. (Specification
4, Figure 2A). The use of these two clock signals permits the
operations on the IC to proceed faster than if they relied solely
on the system clock. To keep operations properly
synchronized, however, it is important that the two clock signal
not overlap each other. Since clock signals degenerate as they
traverse the IC, it is useful to be able to adjust the clock speed
so that the clocks operate as fast as they can, but not so fast that
at any location on the chip the clock signals overlap.
(Specification 3). The invention allows the user to program the
clock speed to achieve this goal, by both hardware means (e.g.
laser burning of delay elements in the clock circuitry to short
them out) and by software means (e.g., control signals to effect
a shorting of the delay elements). (Specification 4 and 5). The
delay elements of each clock generator are placed in the path
where the output of one generator feeds the input of the other.
(Figure 6B).
2. Examiner has rejected the noted claims over the patent to
Walters. Walters teaches placing dual phase clock circuitry on
a Large Scale Integration (LSI) chip “for such logic circuits …
require their own clock generator for generating internal phase
clock signals for their own use.” (Col. 1, ll. 23-25). This
internal clocking can be controlled “for adjusting the clock
overlap voltage either up or down to speed up or slow down a
chip after fabrication. This technique utilizes a laser to break or
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Application 11/111,799

open up fuses connected to electrodes of transistor devices.”
(Col 1, l. 45ff). In Figure 1 of Walters, there is taught a
generator of two clock signals, in which a variable delay is
introduced in the path where the output of one generator (e.g.
#22) feeds the input of the other generator (e.g., #18). (Figure
1).
3. The clock signals in Walters are shown in Figures 3(a), (b) and
(c), where the amount of overlap of the clock signals is
controlled by the techniques of that patent. In Figure 3(b), “it is
desired to decrease the amount of overlap voltage …, the
plurality of fuses F3a-F3n would be blown initially by a laser
cut…” (col 6, ll. 37-39). “As a result, this produces the
minimal amount of overlap voltage between the trailing or
falling edge of the true phase clock signal Ø1 (curve 36a) and
the leading or rising edge of the complementary phase clock
signal Ø2 (curve 38a).” (Col. 6, ll. 53-57).

PRINCIPLES OF LAW
On appeal, Appellants bears the burden of showing that the Examiner
has not established a legally sufficient basis for the rejection of the claims.

“In reviewing the [E]xaminer’s decision on appeal, the Board must
necessarily weigh all of the evidence and argument.” In re Oetiker, 977
F.2d 1443, 1445, 24 USPQ2d 1443, 1444 (Fed. Cir. 1992).
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Application 11/111,799

Both anticipation under 35 U.S.C. § 102 and obviousness under § 103
are two-step inquiries, in which the first step is a proper construction of the
claims and the second step requires a comparison of the properly construed
claim to the prior art. Medichem S.A. v. Rolabo S.L., 353 F.3d 928, 933, 69
USPQ2d 1283, 1286 (Fed. Cir. 2003).

It is axiomatic that anticipation of a claim under § 102 can be found
only if the prior art reference discloses every element of the claim. See In re
King, 801 F.2d 1324, 1326, 231 USPQ 136, 138 (Fed. Cir. 1986) and
Lindemann Maschinenfabrik GMBH v. American Hoist & Derrick Co., 730
F.2d 1452, 1458, 221 USPQ 481, 485 (Fed. Cir. 1984).

Our reviewing court states in In re Zletz, 893 F.2d 319, 321, 13
USPQ2d 1320, 1322 (Fed. Cir. 1989) that “claims must be interpreted as
broadly as their terms reasonably allow.” Our reviewing court further states
that "the words of a claim 'are generally given their ordinary and customary
meaning.'" Phillips v. AWH Corp., 415 F.3d 1303, 1312, 75 USPQ2d 1321,
1326 (Fed. Cir. 2005) (en banc) (internal citations omitted). The "ordinary
and customary meaning of a claim term is the meaning that the term would
have to a person of ordinary skill in the art in question at the time of the
invention, i.e., as of the effective filing date of the patent application." Id. at
1313, 75 USPQ2d at 1326.
To serve as anticipation when the reference is silent about the asserted
inherent characteristic, such gap in the reference may be filled with recourse
to extrinsic evidence. Such evidence must make clear that the missing
descriptive matter is necessarily present in the thing described in the
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reference, and that it would be so recognized by persons of ordinary skill.
Continental Can Co. USA Inc. v. Monsanto Co., 948 F2d 1264, 1268, 20
USPQ2d 1746, 1749 (Fed. Cir. 1991)

ANALYSIS
Appellants contend that Examiner erred in rejecting claims 20, 21, 23,
26-28, 30, and 33 under 35 U.S.C. § 102(e). Reviewing the findings of facts
cited above, and the application of the Walters reference to the limitations of
the claims as recited in the Answer (Pages 3 and 4), we find that the
Examiner has made a prima facie case for the rejection, having located in the
Walters reference elements associated to the claimed limitations. However,
the Appellants have raised three challenges to the rejection.
First, Appellants contend that the Examiner erred in applying the
Walters reference, as the clock generator in that reference “allows the
amount of voltage overlap between two CMOS phase clock signals to be
adjustably increased or decreased, but never eliminated.” (Br. 14). They
cite Figure 3(b) of Walters:

Curves indicating decline of Ø1 and rise of Ø2

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The Examiner argues that separating the clock pulses is the very
essence of the Walter reference, and thus it is a valid reference (apparently
the little overlap at the bottom of Fig. 3(b) notwithstanding). (Answer 4).
Secondly, he argues that independent claims do not require that the
“overlapping between the output clock signals be eliminated.” (Answer 5,
top). The Appellants strenuously object to this interpretation of the claims.
(Reply Br. 2).
Considering the limitations of Claim 20, the key phrase is “wherein
the coupling of delay elements along the first feedback path controls the
amount of time that clock edges associated with the first and second clock
outputs are non-overlapping”. Both this limitation, and its counterpart in
method claim 27, call for the delay elements being able to control the
amount of time that clock edges are non-overlapping. This limitation,
however, does not absolutely require that the pulses ever be non-
overlapping, but rather that the controls merely be in place to establish the
amount of non-overlapping.
We agree with the Examiner’s first argument that the term “clock
edges” can be broadly but reasonably read on the top corners of the clock
pulses of Walter, as thereafter the pulses decline rapidly below a threshold of
effectiveness. Furthermore, a second point to consider is that even Figure
3(b) indicates a time in which the clock edges are non-overlapping -- namely
from the top right hand corner of pulse 36a to the point where line 38a starts.
Since 38a does not exist in that region, the lines are non-overlapping. In
addition, there is another span of time in this cycle in which the outputs are
non-overlapping, namely from the point when 36a ceases to exist, onward to
a later point of 38a. As can be seen by the various Figures 3(a), (b), and (c),
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the delay elements control the amount of time that those periods of non-
overlap occur. Although the delay elements control periods in which the
outputs overlap, they nevertheless necessarily control periods of non-overlap
as well. We thus do not find error in the rejection for Appellants’ first
reason.
Appellants next argue that “eliminating a transistor in Walters does
not necessarily add or reduce any sort of delay along lines 24 or 26 [the
feedback paths] in Walters …, thus the transistors are not “delay elements”.
(Br. 18, middle). In the footnote at the bottom of the page, Appellants
remind us that a delay element, according to the Specification, may be
“inverters or any device (i.e. resistors) that delay a signal”. (Br. 18 n.1)
Certainly the fuses and associated transistors in Walters are devices, and
their purpose and operation are to cause the respective lagging and leading
of the clock signals by controlled amounts. (Walters, Col. 6, middle). We
find that they can fairly be read on the delay elements.
Finally, Appellants argue that the claim requires “a first plurality of
delay elements in series along the …feedback path”. Pointing to Figure 4 of
Walters, Appellants argue that the delay elements are arranged in parallel,
not in series. (Br. 18 middle). While it is true that the individual elements
are arranged in parallel with each other, the block of them is arranged in
series in the feedback paths 24 and 26, as is readily noticed in Figure 1.
For the foregoing reasons, we conclude that Appellants have not
found reversible error in the rejection of claims 20, 21, 23, 26-28, 30, and
33.

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CONCLUSION OF LAW
Based on the findings of facts and analysis above, we conclude that
the Examiner did not err in rejecting claims 20, 21, 23, 26-28, 30, and 33.
The rejection of those claims is affirmed.

DECISION
The Examiner's rejection of claims 20, 21, 23, 26-28, 30, and 33 is
Affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

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AFFIRMED

eld

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