Ex Parte Trivedi et alDownload PDFPatent Trial and Appeal BoardMar 19, 201813690080 (P.T.A.B. Mar. 19, 2018) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 13/690,080 11130/2012 144016 7590 03/21/2018 Sheridan Ross P.C. 1560 Broadway, Suite 1200 Denver, CO 80202 FIRST NAMED INVENTOR Manish Trivedi UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. Ll2-1410US1 4262 EXAMINER TRA, ANH QUAN ART UNIT PAPER NUMBER 2842 NOTIFICATION DATE DELIVERY MODE 03/21/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): e-docket@sheridanross.com mreno@sheridanross.com mellsworth@sheridanross.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte MANI SH TRIVEDI and MANI SH UMEDLAL PATEL Appeal2016-006497 Application 13/690,080 Technology Center 2800 Before KAREN M. HASTINGS, MICHAEL P. COLAIANNI, and SHELDON M. McGEE, Administrative Patent Judges. COLAIANNI, Administrative Patent Judge. DECISION ON APPEAL Appeal2016-006497 Application 13/690,080 Appellants appeal under 35 U.S.C. § 134 the final rejection of claims 1, 2, 4, 5, 7, 9-17, and 20-24. We have jurisdiction over the appeal pursuant to 35 U.S.C. § 6(b). We AFFIRM. Appellants' invention is directed to a latch circuit comprising a true node, a complement node, true node setup circuitry, complement node setup circuitry, and amplification circuitry (Spec. ,-i 2; claim 1 ). Claim 1 is illustrative: 1. An apparatus comprising a latch circuit comprising: a clock signal; a complement clock signal; an input data signal that provides an input data value having a logic high value and a logic low value; a high-voltage reference source having a first voltage; a low-voltage reference source having a second voltage, wherein the first difference in voltage between the high-voltage reference source and the low voltage reference source is greater than a second difference in voltage between the logic high value and the logic low value of the input data signal; a true node; a complement node; true node setup circuitry comprising a first transistor coupled to the true node and the input data value, wherein the first transistor is gated by either the clock signal or the complement clock signal, and wherein the first transistor is configured to selectively connect the true node to the input data value; complement node setup circuitry comprising: a second transistor coupled to the complement node and the output of a third transistor and a fourth transistor, wherein the second transistor is gated by either the clock signal or the complement clock signal, and wherein, based on either the clock signal or the complement clock signal, the second transistor connects the complement node to the low-voltage reference source or the high-voltage reference source through the third transistor and/or the fourth transistor; the third transistor coupled to the high-voltage reference source and the second transistor, wherein the third transistor is gated by the input data 2 Appeal2016-006497 Application 13/690,080 signal, and wherein, based on the input data signal, connects the second transistor to the high-voltage reference source; the fourth transistor coupled to the low-voltage reference source and the second transistor, wherein the fourth transistor is gated by the input data signal, and wherein, based on the input data signal, connects the second transistor to the low-voltage reference source; wherein the complement node setup circuitry is configured to selectively connect the complement node to either the high-voltage reference source or the low-voltage reference source based on the input data value and the clock signal or the complement clock signal; and amplification circuitry coupled to the true node and the complement node, the clock signal, the high-voltage reference source, and the low- voltage reference source, wherein the amplification circuitry comprises: cross coupled inverters, wherein each inverter comprising a P-type transistor and an N-type transistor; a fifth transistor coupled to the low-voltage reference source and channels of the N-type transistor of each inverter, wherein the fifth transistor is gated by either the clock signal or the complement clock signal, and wherein, based on by either the clock signal or the complement clock signal, connects the channels of the N-type transistor of each inverter to the low- voltage reference source; wherein the high-voltage reference source is coupled to channels of the P-type transistor of each inverter; wherein the amplification circuitry is configured to amplify a voltage differential between the true node and the complement node by driving the true node toward the first voltage of the high-voltage reference source when the input data signal is at the logic high value and by driving the complement node to toward the second voltage of the low voltage reference source when the input data signal is at the logic high value; and during amplification of the voltage differential by the amplification circuitry, the true node setup circuitry isolates the true node from the input data value and the complement node setup circuitry isolates the complement node from the high-voltage reference source and the low-voltage reference source. Appellants appeal the following rejections: 1. Claims 1, 2, 4, 5, 7, 9-17, and 20-24 are rejected under 35 U.S.C. § 112, first paragraph, as failing to comply with the written description requirement. 3 Appeal2016-006497 Application 13/690,080 2. Claims 1, 2, 4, 5, 7, and 9-15 are rejected under 35 U.S.C. § 103(a) as unpatentable over Bruccoleri (US 5,808,488 issued September 15, 1998) in view of Mak (US 2006/0168487 Al, published July 27, 2006) and Kossel (US 2009/0033401 Al, published February 5, 2009). 3. Claims 16, 17, and 20-24 are rejected under 35 U.S.C. § 103(a) as unpatentable over Watanabe (US 2004/0062086 Al, published April 1, 2004) in view of Bruccoleri, Mak and Kossel. FINDINGS OF FACT & ANALYSIS REJECTION (1 ): Written Description The Examiner finds that the original Specification fails to teach that the first difference in voltage between the high-voltage reference source and the low voltage reference source is greater than a second difference in voltage between the logic high value and the logic low value of the input data signal (Final Act. 2). Appellants argue that Figure 2 of the Specification supports that the "spread between DT and DC, when pulled toward VDD and VSS respectively, is much greater than the spread between the low value of D at time tl and the high value of D at time t6, for example" (Br. 12). Appellants contend that the only way to effect amplification that occurs by drawing DT and DC to the high voltage reference (VDD) and the low voltage reference (VSS) is if the voltage difference between VDD and VSS is greater than the voltage difference between the high value of the input data signal D and the low value of the input data signal D (Br. 11 ). Appellants contend that one of 4 Appeal2016-006497 Application 13/690,080 ordinary skill in the art would have known that the drawing of the voltage would not be possible unless the voltage relationship as recited in the claim was met (Br. 10-11 ). To satisfy the written description standard, the Specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor had possession of the claimed invention. Moba, B. V. v. Diamond Automation,Inc., 325 F.3d 1306, 1319 (Fed. Cir. 2003). In the present case, the preponderance of the evidence favors the Examiner's finding of lack of written description. Specifically, the Examiner finds that the amplification of the signal by drawing DT or DC signal to a VDD or VSS voltage does not require the particular voltage difference recited in the claim (Ans. 3). The Examiner finds that a "unity gain amplifier" amplifies the difference between the input voltage to generate a "difference output" voltage that is equal to the difference between the high voltage level and low voltage level of data signal D (Ans. 3). The Examiner further finds that the spread in voltage depicted in Appellants' Figure 2 only shows the "slew rate" of the amplifier, not the amplitude (or peak-to-peak amplitude) of the signals (Ans. 3). The Examiner finds that Appellants' Figure 2 shows "that the amplitude of input data D is equal to the amplitude of signals DT and DC, not less than the amplitude of signal DT and DC as claimed" (Ans. 3). Appellants do not dispute or otherwise show reversible error in these findings of the Examiner (No Reply Brief filed). On this record, the Examiner has put forth a reasonable basis to find that Appellants were not in possession of the claimed voltage relationship. 5 Appeal2016-006497 Application 13/690,080 We affirm the Examiner's 35 USC§ 112, first paragraph, rejection for lack of written description. REJECTIONS (2) and (3): Obviousness Appellants' arguments focus on the subject matter of claim 1 (Br. 13- 18). Appellants do not separately argue independent claim 16 other than to say that W atanbe does not cure the argued deficiencies of Bruccoleri, Mak, and Kossel (Br. 17-18). Therefore, non-argued claims will stand or fall with claim 1. The Examiner's findings and conclusions regarding Bruccoleri, Mak and Kossel are located on pages 3 to 5 of the Final Action. The Examiner finds that Bruccoleri teaches most of the limitations of claim 1, except for the latch circuit generating a VIN- signal and the voltage difference relationship between the high-voltage reference source and low voltage reference source (Final Act. 3, 5). The Examiner finds that Mak's Figure 3 shows a similar latch circuit that uses inverter 31 coupled to data signal D to generate an inverted data signal (Final Act. 3). The Examiner finds that Kossel teaches in Figure 2 a latch circuit that amplifies input data that has a high logic value that is lower than the high voltage reference VCC of the latch circuit (Final Act. 5). The Examiner concludes that it would have been obvious to use Mak's CMOS inverter for Bruccoleri's buffer BFl coupled to a VIN+ signal to generate VIN- for the purpose of saving space and cost (Final Act. 3). The Examiner further concludes that it would have been obvious to use Mak' s Figure 3 to amplify a data signal that has a high logic value that is lower than the high voltage reference V cc of the latch circuit in Figure 3 for the purpose of level shifting the data signal (Final Act. 5). The 6 Appeal2016-006497 Application 13/690,080 Examiner determines that Bruccoleri's modified Figure 4 shows that the first difference in voltage between the high-voltage reference source and the low voltage reference source is greater than a second difference in voltage between the logic high value and the logic low value of the input data signal (Final Act. 5). Appellants argue that Bruccoleri, Mak and Kossel do not individually or as combined teach a complement node as recited in claim 1 (Br. 14). Appellants argue that one of ordinary skill in the art would not have substituted Mak's inverter 31 for Bruccoleri's buffer BFl because buffer BF 1 has a different function compared to and a different configuration from inverter 31 (Br. 15). Appellants contend that Bruccoleri's buffer BFl modifies the node voltage and does not function as a simple inverter (Br. 15). Appellants argue that the Examiner has not explained how Kossel's teaching to amplify the output of a latch circuit would have been combined with Bruccoleri as modified by Mak (Br. 15). Appellants argue that Kossel does not teach complement node circuitry (Br. 15). The preponderance of the evidence favors the Examiner's obviousness conclusion. The Examiner finds that Bruccoleri's buffer BFl functions as an inverter like Mak' s inverter 31 such that one skilled in the art would have been motivated to use Mak's inverter 31 for buffer BFl in order to save space and because they are equivalents (Ans. 5). The Examiner provides a reasoned analysis that supports the finding that Bruccoleri' s buffer BFl functions as an inverter (Ans. 5). Appellants rely on Bruccoleri's disclosure at column 3, lines 4 to 17 as teaching that buffer BFl does not function as an inverter (Br. 15). Appellants do not explain why that portion of Bruccoleri fails to teach that the buffer BF 1 functions as an 7 Appeal2016-006497 Application 13/690,080 inverter. Indeed, Figure 2 of Bruccoleri which corresponds to the portion of column 3 argued by Appellants shows that BFl has the circuit symbol (i.e., a triangle with a circle at one of the triangle's apices) of an inverter. We are unpersuaded by Appellants' argument regarding the Examiner's application of Kossel. The Examiner relies on Kossel to teach a latch circuit that amplifies input data that has a high logic value that is lower than the high voltage reference V cc of the latch circuit (Final Act. 5). The Examiner concludes that Bruccoleri as modified by Mak and Kossel would have suggested that complement nodes are pulled to a different voltage in light of Kossel's teaching that output signals have amplitude higher than the amplitude of input signals (Ans. 4). The Examiner is not relying on Kossel to teach the complement node circuitry as argued by Appellants. Rather, the Examiner relies on Kossel to teach that is known to operate a latch circuit so as to satisfy the claim limitation that the first difference in voltage between the high-voltage source and the low-voltage reference source is greater than a second difference in voltage between the logic high value and the logic low value of the input data signal (Final Act. 5). Appellants do not dispute the Examiner's specific finding in that regard. Furthermore, the Examiner has explained that Kossel is used to modify how the amplifier of Bruccoleri as modified by Mak is used (i.e., how it operates) (Final Act. 5). In other words, Bruccoleri in view of Mak meets the structure of Appellants' claims and Kossel' s teaching is used to modify how the structure operates. Appellants argue that there is no motivation to combine the teachings of Bruccoleri and Mak (Br. 15). Appellants argue that adding Mak's inverter 31 would increase cost and space required for the circuit (Br. 15). Appellants contend that the latch circuits of Bruccoleri, Mak and Kossel are 8 Appeal2016-006497 Application 13/690,080 all different such that there would have been no reason absent hindsight to combine the teachings of the references (Br. 1 7). Appellants argue that to change the pulse latch of Mak into the latch of Bruccoleri and futher include the level shifter of Kossel would require a complete redesign of one or all of Bruccoleri, Mak and Kossel and would have rendered each patent unsuitable for its intended purpose (Br. 16-17). Contrary to Appellants' arguments, the Examiner is not proposing to change the pulse latch of Mak into Bruccoleri's latch. Rather, the Examiner proposes modifying Bruccoleri's latch by substituting Mak's inverter for Bruccoleri's buffer BFl that functions as an inverter. Kossel is merely relied upon to teach that that it would have been obvious to use Bruccoleri's structure as modified by Mak in a manner that satisfies the voltage relationships in claim 1 (Final Act. 5). In other words, Appellants have not persuaded us that a substantial redesign of the structure would have been required to substitute Mak's inverter for the buffer BFl in Bruccoleri's latch circuit. The Examiner also finds that Bruccoleri and Mak are directed to using differential signals such that one of ordinary skill in the art would have been motivated to use an inverter coupled to receive Bruccoleri's VIN+ to generate VIN- for the purpose of saving space and cost (Ans. 4-5). Appellants do not contest this reason provided by the Examiner for combining the teachings of Bruccoleri and Mak (No Reply Brief filed). The Examiner also finds that using an inverter rather than another circuit to generate signal VIN- would save, not increase, space and cost (Ans. 6). Appellants provide no evidence that using Mak's inverter would increase the space and cost of Bruccoleri' s latch circuit. 9 Appeal2016-006497 Application 13/690,080 On this record, we affirm the Examiner's§ 103 rejection over Bruccoleri in view of Mak and Kossel and the§ 103 rejection over Watanabe in view of Bruccoleri, Mak and Kossel. DECISION The Examiner's decision is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 3 7 C.F .R. § 1.13 6( a)( 1 ). ORDER AFFIRMED 10 Copy with citationCopy as parenthetical citation