Ex Parte TranDownload PDFPatent Trial and Appeal BoardJun 4, 201411211911 (P.T.A.B. Jun. 4, 2014) Copy Citation UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/211,911 08/24/2005 Luan C. Tran MI22-2985 6073 21567 7590 06/05/2014 Wells St. John P.S. 601 West First Avenue Suite 1300 Spokane, WA 99201-3828 EXAMINER LIN, JOHN ART UNIT PAPER NUMBER 2815 MAIL DATE DELIVERY MODE 06/05/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ________________ Ex parte LUAN C. TRAN1 ________________ Appeal 2012-005233 Application 11/211,911 Technology Center 2800 ________________ Before ROMULO H. DELMENDO, MARK NAGUMO, and DONNA M. PRAISS, Administrative Patent Judges. PRAISS, Administrative Patent Judge. DECISION ON APPEAL 1 The real party in interest is listed as Micron Technology, Inc. (Appeal Brief, filed 22 September 2011 (“App. Br.”), 3.) In the absence of page numbering in the Appeal Brief, we adopt the convention of referring to the title page as page number 1 and numbering the pages in that sequence. Appeal 2012-005233 Application 11/211,911 2 Appellant timely appeals under 35 U.S.C. § 134(a) from the final rejection2 of claims 22-24, 26-28, 65, 70-72, and 74-77. We have jurisdiction. 35 U.S.C. § 6. We affirm. OPINION A. Introduction3 The subject matter on appeal relates to semiconductor constructions, and specifically semiconductor constructions that are “suitable for electrical isolation in an integrated circuit construction.” Spec. [0001], [0004]. It is said that “[e]lectrical isolation is commonly utilized in semiconductor constructions to alleviate, or prevent, leakage between electrical devices. . . . (such as, for example, access transistor constructions).” Id. at [0002]. Facets that influence leakage currents between transistor devices are said to include “junction leakage in source/drain regions; drain-induced barrier lowering (DIBL) due to short gate lengths; gate-induced drain leakage (GIDL) due to high electric fields in a gate overlap region; narrow-width effects; and stress-induced leakage current (SILC) due to a proximity of an isolation region to a device.” Id. 2 Office Action mailed 13 April 2011 (“Final Rejection”; cited as “FR”). 3 Application 11/211,911, Semiconductor Constructions and Methods of Forming Semiconductor Constructions, filed 24 August 2005 as a division of 10/367,520, filed 13 February 2003, now U.S. Patent 7,157,775, claiming the benefit of divisional application 10/229,336, filed 26 August 2002, now U.S. Patent 6,756,619. The specification is referred to as the “911 Specification,” and is cited as “Spec.” Appeal 2012-005233 Application 11/211,911 3 Claim 22 is representative and reads: A semiconductor construction comprising: a semiconductive material substrate; a first and a second transistor construction over the semiconductive substrate material, each of the first and second transistor constructions having opposing sidewalls with a pair of insulative spacers along the sidewalls; an isolation gate structure having a gate width disposed between the first and second transistor constructions, the isolation gate structure comprising a heavy p-type doped pocket region substantially centrally beneath the isolation gate, the doped pocket region having a width that is less than or equal to the gate width, the isolation gate being disposed directly on the doped pocket region; a first and a second source/drain region within the substrate, the first transistor construction being disposed between the first and the second source/drain regions, a first end of the first source/drain region extending beneath the spacer on a first side of the first transistor construction and the second source/drain region extending beneath the spacer on an opposing second side of the first transistor construction; a third and a fourth source/drain region within the substrate, the second transistor construction being disposed between the third and fourth source/drain regions, a first side of the fourth source/drain region extending beneath the spacer on a first side of the second transistor construction, and the third source/drain region extending beneath the spacer on an opposing second side of the second transistor construction; the first, second, third and fourth source/drain regions being commonly doped with a first type of dopant; and a source/drain extension associated with the first side of the first source/drain region, the source/drain extension being doped with a second type of dopant and extending Appeal 2012-005233 Application 11/211,911 4 the first side of the first source/drain region farther beneath the first transistor construction; extensions being absent from a second side of the first source/drain region, and absent from the second source/drain region. (Claims Appx., App. Br. 14-15; key limitations in dispute italicized.) The Examiner maintains the following grounds of rejection:4 A. Claims 22, 24, 65, 70-72, and 74-77 stand rejected under 35 U.S.C. § 103(a) over the combined teachings of Chan,5 Wang,6 and Shin.7 B. Claims 23 and 26 stand rejected under 35 U.S.C. § 103(a) over the combined teachings of Chan, Wang, Shin, and Shih.8 C. Claims 27 and 28 stand rejected under 35 U.S.C. § 103(a) over the combined teachings of Chan, Wang, Shin, and Yoh.9 D. Claims 66-68 stand rejected under 35 U.S.C. § 103(a) over the combined teachings of Chan, Wang, Shin, and Akram.10 B. Discussion Findings of fact throughout this Opinion are supported by a preponderance of the evidence of record. The Examiner finds that Chan’s Figure 9 discloses all of the limitations of claim 22 except for the required source/drain extension (Ans. 4 Examiner’s Answer mailed 6 December 2011 (“Ans.”). 5 U.S. Patent 5,849,614 issued 15 December 1998. 6 U.S. Patent 6,284,579 B1 issued 4 September 2001. 7 U.S. Patent 5,904,530 issued 18 May 1999. 8 U.S. Patent 6,232,160 B1 issued 15 May 2001. 9 U.S. Patent 4,553,098 issued 12 November 1985. 10 U.S. Patent 6,451,658 B2 issued 17 September 2002. Appeal 2012-005233 Application 11/211,911 5 6) and a heavy p-type doped pocket region substantially centrally beneath the isolation gate (id. at 7). The Examiner determines it would have been obvious to modify the semiconductor construction of Chan to include a source/drain extension associated with the first side of the first source/drain region and absent from both the second side of the first source/drain region and the second source/drain region for the purpose of reducing leakage current as taught by Wang. Id. (citing Wang Fig. 3 (doped pocket 20), col. 3, ll. 35-51.) The Examiner also determines it would have been obvious to modify Chan to include the isolation gate structure to comprise a heavy p- type doped pocket region substantially centrally beneath the isolation gate to prevent short channel effects as taught by Shin. Id. at 7-8 (citing Shin Fig. 3e, col. 3, ll. 25-67.) Appellant does not dispute the Examiner’s findings regarding Chan. See generally App. Br. In Appellant’s view, the Examiner failed to establish a prima facie case of obviousness because “the Office does not provide any rationale for the particular pattern recited [in independent claims 22, 65, and 72] relative to alternative patterns, rather the Office only provides motivation for providing an extension.” App. Br. 11. Appellant further argues that none of Chang, Wang, or Shin teach a “doped pocket region beneath an isolation structure.” Id. Specifically, Appellant argues that “the teachings of Shin are specific to active transistors and no motivation has been provided for modification of Chan’s isolation structure rather than active transistors.” Id. The Examiner responds that “Wang discloses a source/drain region extension with an absence of source/drain region extension on the opposing Appeal 2012-005233 Application 11/211,911 6 side of the transistor.” Ans. 16. The Examiner cites Figure 3 of Wang shown below: (Figure 3 is a cross-sectional view of a substrate and a transistor in a microelectronics fabrication.) Referring to Figure 3, above, the Examiner finds “[s]ince Wang discloses having the doped pocket 20 only on one side of the transistor [12], the other side of the transistor would inherently not have a doped pocket.” Id. at 17. Regarding the combination of Shin with Chan, the Examiner responds [s]ince the purpose of the isolation gate structures of Chan are to prevent the region below them from conducting, adding the ion implantation layer 19 of Shin to prevent short channel effects, such as punch through, would provide further isolation properties. Therefore it would be beneficial to have modified Chan to have an ion implantation layer under the isolation gate structures to have further isolation properties. Id. Appellant provides no response to the Examiner’s finding that adding Shin’s ion implantation layer under the isolation gate would provide further isolation properties, which we find reasonable. The issue dispositive of this appeal is whether claim 22 is sufficiently broad as to the recited “a first and a second source/drain region”, “a third Appeal 2012-005233 Application 11/211,911 7 and a fourth source/drain region”, and first and second sides of the first source/drain region such that Wang’s disclosure of a source/drain extension on one side of a first source/drain region, the absence of a source/drain extension on the other side of a first source/drain region, and the absence of a source/drain extension from the second source/drain region in combination with the semiconductor of Chan, with Shin’s p-doped layer beneath a gate structure, encompasses the claimed pattern. We begin with the language of the claim itself, consulting the supporting Specification for definitions and to determine whether persons of ordinary skill in the art would have attributed to particular words or phrases specialized meanings distinct from the general meaning of those words or phrases in everyday use. Cf. In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). Here, “first”, “second”, “first side”, and “second side” are, on their face, broad limitations, particularly in the absence of disclosure of spatial and temporal variations on the selection of a first source/drain region or side relative to a second source/drain region or side. Appellant directs us to Figure 22, the first, second, third and fourth source/drain regions numbered 34 in Figure 22, and paragraphs 102 through 104 as support for the extensions and the absence of extensions in claim 22. App. Br. 4-5. Claim 22, however, does not require any particular arrangement of the first, second, third, and fourth source/drain regions relative to each other, nor does claim 22 require any particular orientation where the extensions are located or not located on a first source/drain region. Appeal 2012-005233 Application 11/211,911 8 The semiconductor construction shown in Figure 22 of the Specification is reproduced below: Figure 22 above is a cross-sectional view of a semiconductor wafer construction that refers to the first, second, third, and fourth source/drain regions generically by the number 34 located between the transistors 14, 16 and the isolation gate 36. See Spec. ¶ [0047], [0057], [0103]; cf. App. Br. 4 (the number 32 is identified mistakenly as both the spacer and the source/drain regions). Figure 22 likewise does not require any particular orientation of the first, second, third, and fourth source/drain regions to each other or relative to a first and a second side of a first source/drain region. Even if Figure 22 were to require that the first side of the first source/drain region was located on the right side of the first source/drain region, we will not read limitations from specific embodiments into the claims. In re Am. Acad. Of Sci. Tech Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004). Appeal 2012-005233 Application 11/211,911 9 In the Reply Brief,11 Appellant argues that “each of the independent claims of the application recites a pair of transistors each having a single extension. Wang makes no teachings or suggestions relative to a second transistor and therefore cannot suggest the recited pattern of extensions with respect to two transistors.” Reply Br. 1. This argument is not persuasive for a number of reasons. First, the Examiner relies on Chan rather than Wang for teaching the semiconductor construction having multiple transistors, which Appellant does not dispute. Second, claim 22 only requires that an extension be present on one side of a first source/drain region and absent from the other side of the first source/drain region as well as absent from the second source/drain region. Appellant does not dispute these limitations are met by Wang’s Figure 3. (Claim 22 does not require that the source/drain extension associated with the first side of the first source/drain region be located to the left of the transistor as shown in Figure 22 of the Specification under the transistor located on the far left. Nor does claim 22 require that the source/drain extension associated with the first side of the first source/drain region be located to the right of the transistor as shown in Wang and in Figure 22 of the Specification under the transistor located to the far right.) Third, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 426 (CCPA 1981); In re Merck & Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986). Appellant has not presented substantively distinct arguments for the patentability of other claims other than to assert that “no motivation exists 11 Reply Brief filed 8 February 2012 (“Reply Br.”). Appeal 2012-005233 Application 11/211,911 10 for substituting the gate materials disclosed by Akram for those disclosed by Chan” in support of dependent claims 66-68 on the grounds that “[i]ndication that the materials are suitable for gate materials is insufficient motivation for combining with the recited doped extensions and doped pocket region.” See App. Br. 12. Appellant’s additional argument regarding the substitution of the specific gate materials taught by Akram for the gate structures in Chan is not persuasive because Appellant has not directed us to any credible evidence that the level of skill in the art indicated by the applied references is such that undue experimentation would have been required to use known gate materials disclosed in one semiconductor for another. Nor has Appellant argued for patentability based on unexpected results or other so-called secondary considerations. We conclude that harmful error has not been demonstrated in the Examiner’s rejections. C. Order We affirm the rejection of claims 22-24, 26-28, 65, 70-72, and 74-77. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). AFFIRMED kmm Copy with citationCopy as parenthetical citation