Ex Parte Tran

Board of Patent Appeals and Interferences

Mar 27, 2012

11095681 (B.P.A.I. Mar. 27, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte THANG MINH TRAN
____________

Appeal 2009-013328
Application 11/095,681
Technology Center 2100
____________

Before JOHN A. JEFFERY, THOMAS S. HAHN, and DENISE M.
POTHIER, Administrative Patent Judges.

POTHIER, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-17 and 19-21. Claim 18 has been canceled. App.
Br. 6. We have jurisdiction under 35 U.S.C. § 6(b). We affirm.

Invention
Appellant’s invention is a technique for avoiding unnecessary fetching
and processing of predicated instructions. A prediction module modifies an
instruction such that an instruction predicated on a conditional statement is
not executed. See Spec. ¶ 0002. Claim 1 is reproduced below with the key
disputed limitations emphasized:
1. A processor, comprising:
an instruction cache module adapted to store a plurality of
instructions, said plurality of instructions comprising a group of
instructions predicated on a conditional statement; and
a branch prediction module coupled to the instruction cache
module and adapted to predict an outcome of the conditional
statement;
wherein, based on said prediction, hardware within the branch
prediction module modifies an instruction preceding the group of
instructions such that at least one instruction in said group of
instructions is not executed;
wherein the hardware modifies said instruction preceding the
group of instructions after said instruction is fetched from the
instruction cache module.

The Examiner relies on the following as evidence of unpatentability:
Gschwind US 6,513,109 B1 Jan. 28, 2003
DeSalvo US 2003/0050933 A1 Mar. 13, 2003

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Gary Scott Tyson, The Effects of Predicated Execution on Branch
Predication, MICRO 27 Proc. of the 27th Annual Int’l Sym. on
Microarchitecture 196-206 (1994) (“Tyson”).

Dionisios N. Pnevmatikatos & Gurindar S. Sohi, Guarded Execution and
Branch Prediction in Dynamic ILP Processors, ISCA ’94 Proc. of the 21st
Annual Int’l Sym. on Comp. Arch. 120-129 (1994) (“Pnevmatikatos”).

THE REJECTIONS
1. Claims 1-4, 6, 7, 16, 17, 19, and 20 are rejected under 35 U.S.C.
§ 103(a) as unpatentable over Gschwind and Pnevmatikatos. Ans. 4-13.1
2. Claim 5 is rejected under 35 U.S.C. § 103(a) as unpatentable over
Gschwind, Pnevmatikatos, and Tyson. Ans. 14-15.
3. Claims 8-15 and 21 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Gschwind, Pnevmatikatos, and DeSalvo. Ans. 15-21.

THE OBVIOUSNESS REJECTION OVER GSCHWIND AND PNEVMATIKATOS
Regarding representative independent claim 1, the Examiner finds that
Gschwind teaches modifying an instruction when bypassing the instruction
to a retirement queue based on Appellant’s definition. Ans. 4, 23-26.
However, the Examiner clarifies that the rejection relies upon Pnevmatikatos
-- not Gschwind -- to teach the recitation for modifying an instruction
preceding a group of instructions predicated on a conditional statement after
the instruction is fetched from the instruction cache module, such that the
instruction is not executed. See Ans. 5-8, 23-25. The Examiner further finds
that: (1) Pnevmatikatos’ executing guard instructions and its resulting

1 Throughout this opinion, we refer to (1) the Appeal Brief filed December
29, 2008; (2) the Examiner’s Answer mailed March 13, 2009; and (3) the
Reply Brief filed May 7, 2009.
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behavior (e.g., a jump operation) causes an instruction preceding a group of
instructions to be modified (Ans. 27-29, 32-33, 37, 39-40); (2)
Pnevmatikatos executes a short branch when an instruction is unnecessary
and before the instruction is fetched, which “modifies” instruction i2 (Ans.
30-31); and (3) Pnevmatikatos does not have identical instructions,
especially when dynamically executing the short branch (Ans. 35-36).
Appellant argues that Gschwind does not teach modifying an
instruction, including an instruction fetched from the instruction cache
module as recited. App. Br. 17-22. Appellant also asserts that
Pnevmatikatos: (1) teaches adding instructions to the code or during coding
and before fetching the code from a cache module and uploading into a
computer device (App. Br. 22-26, 29-30); (2) inserts instructions to the
beginning of code to jump over the predicated instructions and does not
modify the instruction (i.e., instruction i2) preceding the group of
instructions after the instruction is fetched from the instruction cache module
as required by claim 1 (App. Br. 23-26); (3) explicitly states that no
instructions are modified and that the instructions are identical in every
respect with the original code (App. Br. 24-27); and (4) uses the guard
instruction to update the bits in the register, but the guard instruction is not
modified and does not cause another instruction to be modified (Reply
Br. 2).

ISSUES
Under § 103, has the Examiner erred in rejecting claim 1 by finding
that Gschwind and Pnevmatikatos collectively would have taught or
suggested hardware that modifies an instruction preceding the group of
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instructions such that: (1) at least one instruction in the group of instructions
is not executed, and (2) modification occurs after the instruction is fetched
from the instruction cache module?

FINDINGS OF FACT (FF)
(1) Appellant states method 298 includes appending a branch
instruction to the instruction (e.g., non-predicated instruction 102) as soon as
the instruction is fetched from the icache 222 (block 318). Spec. ¶ 0031;
Figs. 1-3.
(2) Appellant describes an alternative embodiment where the control
logic 216 appends a binary mask to non-predicated instruction 502. Spec.
¶ 0035; Figs. 2, 4.

ANALYSIS
The crux of this appeal centers on what the claimed phrase, “modifies
an instruction preceding the group of instructions,” means. Appellant
provides examples of modifying an instruction by appending a branch
instruction (FF 1) or a binary mask (FF 2) to that instruction (e.g.,
non-predicated instructions 102, 502) in the disclosure. See also App. Br. 12
nn. 16-17 (citing to paragraphs in the Specification). However, these are just
examples, and claim 1 (as opposed to claim 2) does not recite that the
instruction is modified by appending information to an instruction. The
recitation, “modifies an instruction” in claim 1, is thus not limited to these
described embodiments. See SuperGuide Corp. v. DirecTV Enterprises,
Inc., 358 F.3d 870, 875 (Fed. Cir. 2004).
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As “the words of a claim ‘are generally given their ordinary and
customary meaning[,]’” Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed.
Cir. 2005) (en banc), we refer to a dictionary for a customary meaning of
“modify.” “Modify” is defined as “[t]o change the form or external qualities
of a thing; to shape; to give a new form of being to; as, to modify matter,
light or sound.”2 Thus, giving this term, “modify,” its ordinary and
customary meaning, the phrase, “hardware . . . modifies an instruction,”
means changing the form or quality of an instruction, including but not
limited to appending to the instruction.
Concerning the term, “an instruction,” claim 1 does not limit an
instruction to the instruction that immediately precedes the group of
instructions predicated on a conditional statement. See App. Br. 25. Also,
as broadly as recited, the “instruction” can reasonably be a collection of
instructions that precede the group of instructions predicated on a
conditional statement. Moreover, Appellant has not recited when the
modification occurs other than the modified or changed instruction precedes
the group of instructions predicated on a conditional statement. Thus, as
explained in more detail below, we find the Examiner’s position to be
reasonable that the recited modified instruction is the execution of
Pnevmatikatos’ fetched instructions and the resulting behavior -- not the
code shown in Figure 5 created prior to execution (see Ans. 27-28, 32-33,
37, 39-40). We now turn to the cited art.
Because the Examiner states that the rejection relies entirely on
Pnevmatikatos -- not Gschwind -- to teach the recitation of hardware

2 American Dictionary of the English Language (1828), available at
http://1828.mshaffer.com/d/word/modify.
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modifying an instruction preceding a group of instructions predicated on a
conditional statement after the instruction is fetched from the instruction
cache module (see Ans. 21-24), we will not address Appellant’s arguments
concerning Gschwind failing to teach modifying an instruction (App. Br. 17-
22). As noted by the Examiner (Ans. 5), Pnevmatikatos teaches a processor
that is informed in advance that some instructions will be squashed.
Pnevmatikatos 127. This, at a minimum, teaches or suggests that
Pnevmatikatos' processor receives some information (e.g., an instruction) to
squash later instructions (e.g., instructions i3-i7 are transformed to NOPs
(No Operation Performed)) during execution. See id.
Pnevmatikatos further explains that a scalar mask or shift register
permits the processor to squash unnecessary computations. See id. The
processor identifies unnecessary computations by executing a short branch
(e.g., an instruction), which changes the fetch address and dynamically
transforms instructions to NOPs. See id. Thus, Pnevmatikatos teaches
changing or modifying a fetch address when executing a short branch
instruction (e.g., one resulting behavior as described by the Examiner (see
Ans. 27-28, 32-33, 37, 39-40)) or changes an instruction related to fetching
an address that precedes another group of instructions (e.g., i3-i7). See
Pnevmatikatos 127. Although when this changed or modified fetch address
instruction happens is not explicitly set forth in Pnevmatikatos,
Pnevmatikatos nonetheless teaches or, at least, suggests the modification
will precede the group of instructions in order to squash the instruction
before fetching it, as Pnevmatikatos also teaches. See id.
Additionally, the Examiner finds that an ordinarily skilled artisan
would have understood inserting an instruction (e.g., instruction to transform
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other instructions into NOPs and skip them) immediately after one
instruction is fetched and before another instruction appends an instruction
to another instruction. See Ans. 31, 39. While Appellant argues to the
contrary (App. Br. 26), we agree with the Examiner. As discussed above
and consistent with the Examiner’s position (see Ans. 27), an instruction can
be a collection of instructions executed by Pnevmatikatos and the resulting
behavior. Thus, adding the short branch to a collective instruction that
precedes predicated instructions (e.g., i3-i7) modifies the original
instruction. Pnevmatikatos 127. Also, Pnevmatikatos’ execution of the
short branch changes a fetch address and thus modifies an instruction to
fetch a particular address. See id. The execution of the short branch
furthermore transforms an instruction to execute other instructions into
NOPs (e.g., i3-i7) and adds a jump operation. See id. Lastly, all these
changes occur after at least some component (including but not limited to
the short branch) of the original instruction is fetched from the instruction
cache module. See id.
While we acknowledge Pnevmatikatos states that there is no
modification of the existing instructions (see Pnevmatikatos 126), this
statement concerns the assembly code and not its execution. As stated
above, the Examiner maps the executed instructions and the related behavior
to the recited “an instruction preceding the group of instructions[.]” See
Ans. 27. As such, Appellant’s arguments regarding the code’s instructions
transpiring before the code is loaded or fetched (App. Br. 24-25) does not
relate to whether the instructions during execution are modified. Also, what
Pnevmatikatos means by “no modifications to existing instructions” (see
Pnevmatikatos 126), as discussed by Appellant and the Examiner (see App.
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Br. 26-28; Reply Br. 2-3; Ans. 29-30, 34), relates to the assembly code
before execution. Moreover, Pnevmatikatos explains instructions are added
(i.e., AND instruction to set the guard condition in r3 and the use of
GUARD instruction to specify guarding) to the existing instructions and that
the branch instructions are eliminated. See Pnevmatikatos 126-27; Fig. 5.
Thus, these instructions are not identical (see Ans. 30) and the collective
instruction executed before instruction i3 has changed.
In summary, despite Appellant’s assertions (App. Br. 22-30; Reply
Br. 2-3), we find Pnevmatikatos when combined with Gschwind (see Ans. 4-
8) teaches and suggests hardware that modifies an instruction preceding the
group of instructions such that at least one instruction in the group is not
executed and after the instruction is fetched from the instruction cached
module as recited by claim 1.
For the foregoing reasons, Appellant has not persuaded us of error in
the rejection of: independent claim 1 and claims 2-4, 6, 7, 16, 17, 19, and 20
not separately argued with particularity (see App. Br. 17-30).

THE OBVIOUSNESS REJECTION OVER GSCHWIND,
PNEVMATIKATOS, AND TYSON

Regarding claim 5, the Examiner finds that Tyson teaches its
limitations and provides a reason for combining Tyson with the combined
teachings of Gschwind and Pnevmatikatos. Ans. 14-15. Appellant argues
that Tyson: (1) does not cure the alleged deficiencies of Gschwind and
Pnevmatikatos and (2) does not teach the limitations in claim 5. App. Br.
31. We disagree. First, because Gschwind and Pnevmatikatos teach and
suggest all the limitations in claim 1, as discussed above, Tyson need not
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cure any asserted deficiency. Second, as the Examiner correctly points out
(Ans. 41), Appellant has not specifically addressed why Tyson fails to teach
the recited limitation in claim 5. On the other hand, the Examiner has
provided evidence where Tyson teaches these limitations. Ans. 14 (citing to
section 4.3, section 5.1, and Figure 3). Based on the evidence of record
before us, Appellant has not persuaded us of error.

THE OBVIOUSNESS REJECTION OVER GSCHWIND,
PNEVMATIKATOS, AND DESALVO

Independent claim 8 recites similar disputed limitations as claim 1.
Although argued separately, Appellant repeats the arguments presented for
independent claim 1. Compare App. Br. 17-30 with App. Br. 31-42. We are
not persuaded for the reasons discussed above regarding claim 1. Claim 21
is not separately argued but depends from claim 16. However, because
Appellant grouped claim 16 with claim 1 (see App. Br. 30), we are similarly
not persuaded by Appellant’s arguments. For the foregoing reasons,
Appellant has not persuaded us of error in the rejection of: independent
claim 8 and claims 9-15 and 21 not separately argued with particularity
(App. Br. 31-43).

CONCLUSION
The Examiner did not err in rejecting claims 1-17 and 19-21 under
§ 103.

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DECISION
The Examiner’s decision rejecting claims 1-17 and 19-21 is affirmed.
No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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